TSMC
2026-07-13
TSMC CoWoS Capacity to Reach 200k Wafers by 2027, Diversifying from GPU to CPU and ASIC
Summary
Key Takeaways
According to DIGITIMES and Mizuho reports, TSMC has significantly raised its CoWoS monthly capacity guidance: 140,000 wpm by end-2026 (up from 120,000) and 190,000-200,000 wpm by 2027. The supply-demand gap narrows from ~20% currently to ~10% by end-2026, remaining tight in 2027. Third-party OSATs add limited capacity: ASE 20,000 wpm in 2026, 40,000-45,000 wpm in 2027; Amkor 20,000-25,000 wpm by end-2027. TSMC retains >70% of global high-end CoWoS capacity.
Customer structure shifts dramatically: from NVIDIA GPU dominance to a three-driver model (GPU+CPU+ASIC). NVIDIA demand reaches 1,005,000 wafers in 2027 (Blackwell GPU + Vera server CPU); MediaTek demand doubles to 180,000 wafers for its ARM-based AI server CPU using CoWoS-R; Broadcom slightly down to 425,000 wafers (slower Google TPU growth). Server CPU packaging share rises from 11% in 2025 to 24% in 2027. TSMC also advances CoPoS (panel-level packaging) with R&D at VisEra in 2025, material/equipment verification in June 2026, pilot production in 2027, and NVIDIA Feynman platform adoption in 2028-2029. N3 capacity reaches 200,000 wpm in 2027, N2 150,000 wpm, supporting CoWoS wafer demand.
Why It Matters
TSMC's capacity expansion ostensibly meets AI demand but strategically defends against Samsung and Intel's advanced packaging while encircling traditional OSATs (ASE, Amkor). By monopolizing capacity, TSMC locks customers into its ecosystem: once a chip adopts CoWoS design, switching to alternative packaging becomes prohibitively expensive due to physical design coupling.
Hidden physical limitations: CoWoS silicon interposer size is limited by reticle field (~858mm²), constraining die size and HBM stack count (currently max 12, targeting 20/24 by 2028). CoPoS panel-level packaging promises cost reduction but faces warpage control, yield ramp, and material matching challenges, with high uncertainty from pilot to mass production. Moreover, CoWoS cost per wafer remains high (thousands of dollars), and capacity expansion CapEx will be passed to customers, compounding with TSMC's sub-7nm price hikes (8-12%).
PRO Decision
[Vendors] Competitors (Samsung, Intel, ASE, Amkor) should exploit TSMC's CoWoS expansion weaknesses: promote alternative packaging like Samsung I-Cube and Intel EMIB, emphasizing multi-sourcing flexibility and lower switching costs. Target CPU customers (MediaTek) with compatible yet open platforms.
[Enterprises] CIOs and architects should conduct zero-trust audits: require chip vendors to guarantee multi-packaging options (CoWoS, EMIB, I-Cube) in contracts. Include capacity allocation clauses to mitigate TSMC supply risks. Avoid premature lock-in to unproven CoPoS technology.
[Investors] Look beyond TSMC's capacity narrative: the CapEx for expansion will pressure margins, and CoPoS R&D risks may impact long-term profitability. Monitor customer diversification (NVIDIA share decline, MediaTek rise) and OSATs' (ASE, Amkor) potential in differentiated panel-level packaging.
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