TSMC
2026-07-08
TSMC Ramps PIC Capacity to 25K Wafers, CPO Silicon Photonics Poised to Disrupt AI Interconnects
Summary
Key Takeaways
At its 2026 Technology Symposium, TSMC positioned its COUPE platform as critical for reducing latency and power in future AI systems. According to TrendForce and investment analysts, PIC capacity will grow from ~10,000 wafers per month in Q2 2026 to 15,000 in Q4, reaching at least 25,000 wafers per month by 2028.
Initial capacity is limited to NVIDIA, Broadcom, and AMD (2026-2027), with MediaTek and Marvell joining in 2028. The scaling of AI clusters demands higher interconnect bandwidth, pushing CPO beyond lab validation toward mass production. The integration of silicon photonics with advanced packaging will create a comprehensive AI optoelectronic platform, driving demand for FAU, lasers, and optical testing equipment.
Why It Matters
TSMC’s capacity expansion is a strategic move to encircle Intel and Samsung in silicon photonics foundry, locking in NVIDIA, Broadcom, and AMD. The COUPE platform integrates optical engines with advanced packaging (e.g., CoWoS), forcing AI interconnects from electrical SerDes (112G/224G PAM4) to CPO, shifting the electro-optical conversion latency into TSMC’s package and stripping traditional networking vendors (Arista, Cisco) of control plane influence.
Second-order thinking: TSMC downplays CPO’s engineering limitations in hyperscale clusters. PIC yield and laser degradation remain unaddressed; replacing FAU arrays may negate power savings. COUPE solders optical engines onto the package—if a laser fails, the entire GPU module or switch ASIC must be scrapped, creating a significant asset depreciation trap. For flexible topologies like RoCEv2, CPO’s fixed light paths cannot match the reconfigurability of pluggable optics, limiting architectural agility.
PRO Decision
【Competitors (Intel, Samsung, Arista, Cisco)】 Accelerate R&D on silicon photonics foundry or pluggable CPO modules. Intel should leverage its silicon photonics integration to offer a separable laser+modulator solution compatible with TSMC's COUPE, attacking its non-serviceability. Arista and Cisco should jointly develop Linear Pluggable Optics (LPO), emphasizing operational flexibility and depreciation advantages over COUPE's lock-in.
【Enterprises (CIOs and Architects)】 Conduct rigorous TCO audits for CPO-based AI clusters, demand laser MTBF data from vendors, and negotiate optical engine replaceability clauses in procurement contracts to avoid COUPE package lock-in. Prioritize LPO-capable switches and NICs to retain topological flexibility in RoCEv2 networks.
【Investors】 Look past TSMC’s PIC expansion PR. Focus on PIC yield and laser cost data. Near-term beneficiaries are FAU and optical test equipment suppliers (e.g., Coherent, Lumentum), but long-term watch for CPO's asset depreciation trap eroding margins for clients like NVIDIA. Short traditional networking vendors like Arista reliant on pluggable optics, unless they prove LPO ecosystem dominance.
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