Reports
AI-generated structured vendor updates
Meta Iris Chip to Mass Produce in September: 6-Month Cadence Threatens NVIDIA GPU Hegemony
Reuters confirms Meta's Iris AI chip mass production in September, targeting 2.5GW by end-2026 and 14GW by 2027. Meta's 6-month MTIA generation cadence directly challenges NVIDIA's annual GPU cycle, signaling a hyperscaler shift from GPU dependency to custom ASIC sovereignty.
JCET's $1.4B AI Packaging Capex Reshapes Advanced Packaging Supply Chain
JCET announces $1.4B capex for AI advanced packaging in 2026, targeting Chiplet, HBM, 2.5D/3D. This marks Chinese OSAT's major entry into high-end packaging, complementing TSMC's CoWoS expansion and shifting AI packaging from Taiwan-centric to cross-strait division, supporting local hyperscalers' computing needs.
TSMC CoWoS Capacity to Reach 200k Wafers by 2027, Diversifying from GPU to CPU and ASIC
TSMC targets 200k wpm CoWoS capacity by 2027, narrowing supply-demand gap from 20% to 10%. Customer base diversifies from NVIDIA GPU to include AI server CPUs (MediaTek, AMD) and ASICs (Broadcom). CoPoS panel-level packaging enters pilot production in 2027.
Intel押注3D堆叠AI芯片 18A-PT+Foveros Direct 3D+EMIB-T全栈整合
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TSMC Ramps PIC Capacity to 25K Wafers, CPO Silicon Photonics Poised to Disrupt AI Interconnects
TSMC plans to expand its PIC capacity to 25,000 wafers per month by 2028, with its COUPE platform becoming critical for reducing latency and power in AI systems. Initial capacity is allocated to NVIDIA, Broadcom, and AMD, marking CPO's transition from lab to mass production and accelerating the shift from electrical to optical AI interconnects.
NVIDIA Denies Kyber NVL144 Delay, But 78-Layer PCB Bottleneck Exposes AI Hardware Physics Limit
NVIDIA officially denies reports of Kyber NVL144 rack delay to 2028, but SemiAnalysis revelations about a 78-layer ultra-high-density PCB midplane bottleneck and Rubin Ultra cancellation expose hard physical limits in signal integrity and manufacturing, opening a strategic window for AMD and Google.
NVIDIA Kyber NVL144 Delayed to 2028: Midplane PCB Manufacturing Becomes AI Scaling Bottleneck
SemiAnalysis reveals NVIDIA's Kyber NVL144 delayed beyond 12 months to 2028 due to 78-layer Orthogonal Backplane manufacturing challenges. The interim NVL72x2 solution is cancelled due to operational burdens, and the 4-die Rubin Ultra is also scrapped, leaving a product gap in NVIDIA's scaling roadmap.
Anthropic in talks with Samsung for 2nm AI chip, targeting NVIDIA CUDA control shift
Anthropic is in early talks with Samsung to manufacture custom AI chips using 2nm process and advanced packaging, hiring ex-OpenAI chip engineer Clive Chan. This aims to reduce NVIDIA GPU dependency and seize control of AI infrastructure, signaling a control plane shift in AI compute.
TSMC Adds Winbond to WoW 3D Stacking Memory Supply, Breaking DRAM Oligopoly
Winbond joins TSMC's Wafer-on-Wafer (WoW) 3D stacking advanced packaging supply chain, becoming a new DRAM wafer supplier alongside Samsung, SK Hynix, and Micron. This move reduces reliance on the three global DRAM giants and strengthens AI chip packaging supply resilience. Winbond provides DRAM wafers for vertical stacking with TSMC logic wafers, offering 8GB capacity and 256GB/s bandwidth via its CUBE solution.
TSMC Bets on CoPoS and Glass Substrates: Packaging Paradigm Shifts from Wafer-Level to Panel-Level, AI Chip TCO Inflection
TSMC is replacing CoWoS with CoPoS (panel-level packaging), using 750x620mm square panels and glass core substrates, achieving 20-30% unit area cost reduction. Volume production targets 2028, with AMD Zen 7 as first key customer. This fundamentally alters AI chip packaging economics and capacity scaling.
Google TPU v9 Switches to MediaTek, Breaking Broadcom's AI ASIC Monopoly
Google moves its TPU v9 Humufish design and integration contract from Broadcom to MediaTek, which handles I/O chip design and packaging. Combined with a split-foundry strategy (TSMC N2 compute, Samsung 2nm I/O), this marks a systematic effort to build a multi-vendor, multi-node supply chain, directly dismantling Broadcom's dominance in custom AI ASICs.
TSMC under triple pressure: customer diversification, patent challenges, and EUV strategy shift
TSMC faces operational, legal, and commercial pressures: Google splits Icefish AI chip production with Samsung, US ITC patent probe risks import bans, and resource bottlenecks (labor, water, power) limit expansion. TSMC confirms it will skip high-NA EUV until 2029, using multi-patterning on low-NA EUV for 2nm, saving $5-10B.
MediaTek Pivots to System-Level Integration: Targeting Google TPU and Musk AI Rack Deals
MediaTek elevates its AI strategy from chip design to system-level integration, targeting Google TPU PCBA L6 and Musk AI chip L10 rack assembly. Adopting a light-asset model via Taiwan's supply chain, targeting >40% gross margin, driven by rising complexity from CPO and 800V high-voltage DC power.
MediaTek Shifts from Chip Design to System Integration for Google TPU and Musk's AI Racks
MediaTek upgrades its AI strategy from chip/ASIC design to system-level integration, targeting Google TPU PCBA and Musk's AI chip rack-level (L10) work. Using an asset-light model, it leads design and validation while outsourcing manufacturing, aiming for 40-50% gross margin.
TSMC Accelerates Glass Substrate CoWoS with Japanese and Taiwan Partners
TSMC partners with Ibiden and Innolux to develop glass substrates for next-gen CoWoS packaging. Simulation shows 16% warpage improvement, 27% resistance reduction, targeting AI chip performance and reliability amid competition from Intel and Samsung.
TSMC Reveals Glass Substrate Plan for CoWoS, Marking Packaging Inflection
TSMC publicly disclosed its glass substrate development plan for CoWoS, partnering with Ibiden and Innolux to validate feasibility. Glass substrates offer lower signal loss and higher thermal stability than organic substrates, addressing warpage and signal integrity in large AI chip packaging. Mass production is targeted for 2027-2028, directly competing with Intel's glass substrate roadmap.
Applied Materials Launches Deposition and Etch Systems for 3D Chip Scaling
Applied Materials unveils Centris Spectral SiN ALD for uniform dielectric deposition in GAA contacts and Producer Selectra Mo Etch for molybdenum-based 3D NAND word line separation, addressing high-aspect-ratio uniformity issues critical for AI chip manufacturing.
Intel Foundry Lands Google TPU Packaging Deal: EMIB-T Shakes TSMC's AI Chip Monopoly
Intel secures a multi-billion-dollar deal to package over 3 million Google TPUs using its advanced EMIB-T 2.5D packaging, while the chips themselves remain fabricated at TSMC. This marks Intel's strategic shift from CPU vendor to second-source AI packaging partner, targeting 2028 production. Intel's 18A node yields exceed expectations, but analysts caution the scope is limited to packaging.
TSMC Discloses Glass Substrate Pilot, Packaging Paradigm Shifts
TSMC, with Ibiden and Innolux, publicly discloses glass substrate integration into CoWoS for advanced packaging. Glass offers superior electrical and thermal properties over organic substrates, enabling larger dies and higher density. Mass production is distant; CoPoS remains near-term priority.
Google Awards 3M+ TPU Packaging Orders to Intel Foundry, Breaking TSMC's CoWoS Monopoly
Google has awarded Intel Foundry over 3 million units of next-gen TPU advanced packaging orders, leveraging Intel's EMIB technology with production starting in 2028. This marks Intel Foundry's largest external customer win and a pivotal shift in AI chip packaging away from TSMC's CoWoS monopoly.