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2026-07-13
JCET's $1.4B AI Packaging Capex Reshapes Advanced Packaging Supply Chain
Summary
Key Takeaways
JCET announces $1.4B capex for AI advanced packaging in 2026, focusing on CoWoS-like packaging, Chiplet integration, HBM packaging, and 2.5D/3D technologies. As a Chinese OSAT, JCET will serve local ASIC/HBM packaging needs for Huawei Ascend 910C, Cambricon, Biren, etc. Domestic TGV (Through Glass Via) equipment and 8-inch Gallium Oxide production lines are industrializing.
The investment parallels TSMC's CoWoS expansion to 200K wpm, forming a dual-track capacity expansion. TSMC is expected to hold 70% of high-end CoWoS, with JCET, Amkor, ASE covering the rest 30%. This marks a shift from Taiwan-centric AI packaging to cross-strait division, with synergies among SMIC, Huawei, and JCET. For Chinese hyperscalers (Alibaba, ByteDance, Tencent, Baidu), this supports computing localization and reduces reliance on TSMC's sub-7nm price hikes, leveraging cost advantages of domestic OSAT amid AI compute cost inflation.
Why It Matters
Beneath the surface, this is an ecosystem restructuring move: JCET aims to defend against TSMC's dominance and encircle Amkor/ASE in China's AI packaging market. By tying with Huawei and SMIC, JCET seeks to lock in Chinese hyperscalers' packaging supply.
However, the announcement downplays engineering limitations: 1) CoWoS-like packaging yield and ramp speed lag TSMC, risking higher costs. 2) Domestic TGV and 8-inch GaO equipment unproven, affecting HBM reliability. 3) Chiplet integration lacks deep collaboration with top architects like NVIDIA/AMD, compromising interconnect bandwidth and power efficiency. 4) 2.5D/3D packaging's silicon interposer and hybrid bonding may exceed JCET's linewidth capability, limiting support for 3nm chips. Thus, buyers should carefully assess vendor maturity.
PRO Decision
[Competitors (Amkor/ASE)] Should leverage JCET's technological immaturity, pitching their globally validated CoWoS alternatives (e.g., Amkor's SLIM, SWIFT) with higher yield and faster ramp-up. Offer design service partnerships (Synopsys, Cadence) for Chiplet integration to counter JCET's local supply chain lock-in.
[Enterprises (CIOs/Architects)] When evaluating local AI chips, demand packaging yield data and reliability reports (e.g., HTOL, uHAST) from JCET, comparing against TSMC/Amkor baselines. Avoid single packaging supplier lock-in by planning multi-source packaging options in chip design (compatible bump maps and interposer specs). Monitor domestic TGV/Gallium Oxide equipment mass production validation to mitigate risks of early chip failure.
[Investors] View JCET's $1.4B capex skeptically: advanced packaging has high technical barriers, yield ramp-up takes years, likely pressuring margins. Track customer qualifications (Huawei, Cambricon formal adoption) and technology node (support for 3nm chips). Compared to Amkor/ASE, JCET lags in global customer diversification and advanced node experience, requiring a technology risk discount.
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