Reports
AI-generated structured vendor updates
AMD's Experimental Topological Ghost Protocol Boosts MI300X Inference 10x
AMD introduces experimental Topological Ghost Protocol (TGP) on MI300X GPUs, achieving 431 tokens/sec with 100% success in high-concurrency inference, 10x improvement over standard vLLM. TGP uses KV-cache recycling and segmented state management, still experimental but potentially redefining AI inference benchmarks.
Towards Feature Complete Triton Support in JAX-Triton â ROCm Blogs
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AMD Unveils Zen 6/7 CPU and MI400/500 GPU Roadmap, Targets NVIDIA Rubin with HBM4 and 2nm
AMD unveiled its Zen 6/7 CPU and MI400/500 GPU roadmap at its 2026 Financial Analyst Day, featuring TSMC 2nm process and HBM4 memory. The MI400 series boasts 432GB memory, 19.6TB/s bandwidth, and 40 PFLOPs FP4 performance, directly targeting NVIDIA's Vera Rubin architecture with an annual cadence to disrupt the AI hardware monopoly.
AMD通知AIB合作伙伴上调GPU核心与GDDR捆绑套料出货价约10%
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AMD and NVIDIA Raise GPU Kit Prices by 10%: GDDR Shortage Exposes AI Supply Squeeze
AMD has notified AIB partners of a ~10% price hike on GPU+GDDR bundled kits effective July 2026, following NVIDIA's similar move on RTX 5090 series. The dual price increases stem from severe GDDR supply shortages driven by the AI boom and memory super-cycle, foreshadowing broad retail GPU price increases in H2.
TSMC Hikes Advanced Node Prices 5-10%, Squeezing AI Chip Margins
TSMC informs clients of 5-10% price hikes across all advanced nodes (7nm+), affecting 74% of wafer revenue. Apple, Nvidia, AMD, and others face higher costs, potentially raising AI infrastructure prices.
AMD MI430X GPU Delivers >200 TFLOPS Native FP64, Reshaping HPC-AI Convergence Baseline
AMD powers 4 of top 10 TOP500 supercomputers and previews MI430X GPU with >200 TFLOPS native FP64. This targets AI-for-science workloads, making double-precision compute a key metric for converged HPC-AI infrastructure, directly challenging NVIDIA and Intel.
AMD MEXT Acquisition Turns NAND Flash into DRAM-Class Memory, Halving AI Inference Cost
AMD acquires MEXT, whose technology makes cheap NAND flash behave like expensive DRAM, doubling to quadrupling usable memory capacity while halving costs. This targets inference and agentic AI memory bottlenecks. AMD also signs a 30MW AI compute deployment deal with Rackspace, rolling out from 2026 to 2028.
AMD Silently Drops TSME from Consumer Ryzen: Security Segmentation Locks Enterprise Users
AMD quietly removed Transparent Secure Memory Encryption (TSME) from consumer Zen 5 Ryzen CPUs, reserving it exclusively for Ryzen PRO series. The change, effective from AGESA 1.2.7.0, is hard to detect on Windows but visible on Linux. This security feature segmentation pushes enterprise buyers toward higher-priced PRO SKUs.
AMD Mustang Peak Threadripper: 144 cores, PCIe 6.0, TR6 socket – Power and memory challenges loom
AMD's Zen 6 Threadripper 'Mustang Peak' is confirmed with 2nm TSMC process, DDR5, PCIe 6.0, and a new TR6 socket. Using Powderhorn CCDs, it scales to 144 cores (288 threads) with clocks above 6 GHz. However, massive power draw and memory bandwidth demands (possibly requiring MRDIMM) raise platform cost concerns.
AMD MLPerf 6.0: MI350 GPUs Achieve 3.5x Leap with MXFP4, Debut Multi-Node Training
AMD submitted its most comprehensive MLPerf Training 6.0 results, including first multi-node training (FLUX.1 on 512 GPUs) and MXFP4 training recipe. MI355X delivers 3.5x generational leap over MI300X on Llama 2-70B, within 5% of NVIDIA B200. 10 ecosystem partners validated reproducibility.
AMD Critical RCE Vulnerability Disclosed After 124 Days, Sparks AI Infrastructure Security Crisis
Security researcher mr.bruh publicly disclosed a critical remote code execution (RCE) vulnerability in AMD processors after 124 days without a fix, with AMD refusing a $10,000 bounty. The flaw affects AI servers running AMD EPYC and Instinct, likened to a Log4j moment for AI infrastructure, forcing enterprises to reassess chip-level security response and supply chain risk.
AMD and Rackspace Deploy 30MW Governed AI Stack: Ecosystem Restructuring from Silicon to Outcomes
AMD and Rackspace sign a definitive agreement to deploy 30MW of AMD AI compute (Instinct GPUs including MI355X, EPYC CPUs) across Rackspace's data centers, creating a governed enterprise AI stack with single accountability from silicon to outcomes, targeting regulated industries.
AMD Ryzen 10000 Series to Swap iGPU for NPU: AI Boost at Cost of Basic Display
Leaks suggest AMD's next-gen Zen 6 desktop CPU 'Olympic Ridge' will replace the integrated GPU with an NPU, targeting >40 TOPS for Copilot+ AI PC certification. It also upgrades the client I/O die to support CUDIMM/CAMM and EXPO 1.2 for faster DDR5. The trade-off boosts local AI but forces nearly all users to rely on a discrete GPU for basic display.
AMD Acquires MEXT: AI-Predicted Flash Nears DRAM Performance to Cut AI Memory TCO
AMD acquires MEXT, an AI-driven memory optimization startup. MEXT's predictive technology makes NAND Flash behave like DRAM, expanding effective memory capacity for AI workloads and lowering TCO. The tech will be integrated across AMD's data center portfolio (EPYC, Instinct) to address memory bottlenecks in large models.
AMD Open-Sources AI Software Stack on Vultr, Taking on NVIDIA CUDA Ecosystem
AMD launches a suite of open-source, modular enterprise AI software components on Vultr Marketplace, including AMD Inference Microservices (AIMs), AI Workbench, Resource Manager, and Solution Blueprints. This aims to provide production-grade AI infrastructure without vendor lock-in, directly challenging NVIDIA's CUDA ecosystem.
AMD Backs All-Instinct GPU Cloud: TensorWave's $350M Series B Signals NVIDIA Ecosystem Breakout
TensorWave closes $350M Series B led by Magnetar and AMD Ventures at $1.55B valuation. The cloud is exclusively built on AMD Instinct GPUs (MI300X to MI455X), targeting memory-intensive AI workloads to offer a viable alternative to NVIDIA CUDA lock-in and validate ROCm software stack maturity in production.
AMD Zen 6 Venice 256-Core EPYC Claims 3.3x Rack Performance Over NVIDIA Vera, But Estimates Raise Questions
AMD unveils first estimated performance of Zen 6 Venice EPYC (2nm, 256 cores), claiming 3.3x rack-level integer throughput over NVIDIA Vera at 100kW total power. A direct counter to NVIDIA's Arm push, but based on projected estimates, not silicon.
AMD, Dell, Cambridge Launch UK Sovereign AI Lab to Challenge NVIDIA's CUDA Dominance with Open ROCm
AMD, Dell, and the University of Cambridge launch the Sovereign AI Innovation Lab (SAIL) in the UK, deploying Zenith supercomputer with 5th Gen EPYC and Instinct MI355X GPUs, plus the Sunrise fusion AI system. The lab promotes open, interoperable AI infrastructure based on AMD ROCm, challenging NVIDIA's CUDA lock-in and offering long-term technology choice for national AI initiatives.
AMD EPYC Challenges Rack-Scale Density for Agentic AI Control
AMD claims its EPYC processors lead in rack-scale performance for agentic AI's CPU-intensive services (orchestration, caching, databases). Under a 100kW rack model, EPYC 9965 'Turin' delivers 2.37x throughput over NVIDIA Vera, with next-gen 'Venice' projected at 3.30x. Emphasizes deployability on current x86 platforms, avoiding future architecture dependency.