Reports
AI-generated structured vendor updates
Qualcomm获批AI芯片自动调优专利 应对制造差异
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AMD二季度净利润增超2.5倍，数据中心营收增长107%
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Huawei to Launch Ascend 950DT AI Chip with Native FP8, Doubling Compute Power
Huawei announced the upcoming Ascend 950DT AI chip, doubling compute power versus its predecessor with native FP8 support, improved memory bandwidth, and inter-chip interconnect. Huawei Cloud operates large AI clusters across China, with over 100,000 Ascend accelerators powering autonomous driving training, signaling a push to build a domestic AI ecosystem alternative to NVIDIA.
MediaTek Approves $5B for Data Center AI Chips, First Custom Accelerator to Tape Out in Q4
MediaTek's board has approved a $5 billion self-funded budget to expand into data center AI chips. Its first custom AI accelerator will tape out in Q4 2025, targeting over $2 billion revenue by 2026 and 15-20% market share by 2027. This signals a strategic pivot from mobile SoCs to AI infrastructure.
TSMC Develops EMIB-like Packaging to Challenge Intel and Ease CoWoS Bottleneck
TSMC is developing an EMIB-like advanced packaging technology that uses small silicon bridges instead of large silicon interposers, reducing cost and complexity while easing CoWoS capacity constraints. This move counters Intel's EMIB technology and addresses the growing packaging demands of AI accelerators, securing TSMC's dominance in advanced packaging.
TSMC 2nm Volume Production Begins, AMD First to Launch Venice and MI455X
TSMC has fully ramped its 2nm process at five fabs, contributing ~3% of wafer revenue in Q2. AMD launches the first 2nm-based products: EPYC Venice (256 cores) and Instinct MI455X (320B transistors, 432GB HBM4), shipping in Q3. Samsung targets 1.4nm by 2029, Intel 18A introduces High-NA EUV, intensifying foundry competition.
NVIDIA and SK Group Lock HBM4 Supply and Launch Sovereign AI Factory Model with $500B+ Deal
NVIDIA and SK Group announced a $500B+ AI partnership including a 2GW AI factory using Vera Rubin and HBM4, long-term HBM4 supply lock, and a $1B NVIDIA investment in Naver (with $9B from Brookfield). Samsung and Broadcom signed a $200B deal. This signals a new era of sovereign AI infrastructure and supply chain deep-locking.
AMD Helios Rack Challenges NVIDIA NVLink with Open UALoE Interconnect
At Advancing AI 2026, AMD launched the Helios rack with 72 MI455X GPUs, 18 Venice EPYC CPUs, and Pensando networking, claiming 30% higher inference token/$ vs NVIDIA NVL72. It introduced UALoE open interconnect to break NVLink lock-in, partnering with Cerebras, Cisco, and major AI firms.
AMD Unveils Zen 6 Venice, MI455X, and Helios Rack-Level Design to Challenge NVIDIA
At Advancing AI 2026, AMD launched Zen 6 EPYC Venice (2nm, up to 256 cores) and MI455X (CDNA5, 432GB HBM4, 40 PFLOPS FP4), along with Helios rack reference design (2.9 exaFLOPS FP4 per rack), claiming a 1000x AI performance roadmap, with major commitments from Meta, OpenAI, and others.
AWS推出Grok on Bedrock及新一代AI加速器
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Google's Frozen v2 Chip Hardwires Gemini Architecture for 6-10x TPU Efficiency, Set for 2028
Google is developing Frozen v2, a dedicated AI chip that hardwires the Gemini model architecture into silicon for 6-10x energy efficiency per token over current TPUs. It is a new product line, planned for 2028, with weight update flexibility but a frozen architecture. This validates the industry shift from general-purpose GPUs to dedicated ASICs for AI inference.
Intel Foundry 18A Yields Jump to 85%+; EMIB Packaging Hits 98%, Challenging TSMC N2
Intel Foundry 18A yields surged from 65% to 85%+ in a single quarter, approaching TSMC N2's 90%. EMIB advanced packaging yields reached 90-98%, turning a former bottleneck into a selling point. NVIDIA, AMD, Apple signed on but mostly as secondary suppliers.
TSMC Ramps PIC Capacity to 25K Wafers, CPO Silicon Photonics Poised to Disrupt AI Interconnects
TSMC plans to expand its PIC capacity to 25,000 wafers per month by 2028, with its COUPE platform becoming critical for reducing latency and power in AI systems. Initial capacity is allocated to NVIDIA, Broadcom, and AMD, marking CPO's transition from lab to mass production and accelerating the shift from electrical to optical AI interconnects.
Meta Shifts MTIA ASIC to Samsung 2nm: Ecosystem Restructuring in AI Chip Fab
Meta partners with Samsung for next-gen MTIA ASIC production, moving from TSMC to Samsung 2nm node. Targeting hundreds of thousands of units to support 5GW data center goal by 2030, with new chip every six months, restructuring the AI chip supply chain ecosystem.
Qualcomm Enters AI Inference with Dragonfly C1000 CPU and HBC Near-Memory Compute
Qualcomm unveils Dragonfly roadmap with Oryon-based C1000 CPU and AI300 inference accelerator featuring HBC near-memory compute. Meta and Microsoft are early adopters. The strategy targets AI inference TCO reduction and memory wall breakthrough, bypassing Nvidia's training dominance.
Qualcomm Enters AI Datacenter with Dragonfly ARM CPU, Meta Signs Multi-Generation Deal
Qualcomm unveils Dragonfly C1000 ARM-based datacenter CPU, AI300 accelerator, and interconnect. Meta commits to multi-generation CPU supply, Microsoft Azure to deploy HBC chips. Qualcomm targets $15B+ datacenter revenue by FY2029, acquires Modular for software stack.
OpenAI and Broadcom unveil Jalapeño inference ASIC to bypass NVIDIA GPU dependency
OpenAI and Broadcom launch Jalapeño, a custom ASIC for LLM inference, achieving tape-out in 9 months. OpenAI designs architecture, Broadcom provides networking, Celestica handles integration. Planned for large-scale deployment by end-2026 with gigawatt-scale datacenters, aiming to cut inference costs and reduce NVIDIA dependency.
Qualcomm Launches Dragonfly Datacenter Brand, ARM AI Chips Target Intel, AMD, NVIDIA
Qualcomm announced Dragonfly datacenter brand at Computex 2026, including custom ASICs, standard CPUs, and dedicated AI accelerators, extending computing from edge to cloud. First ASIC shipments moved up to 2026. Analysts project $3B revenue in FY2027. This marks Qualcomm's formal entry into the datacenter, challenging X86 and GPU ecosystems.
MediaTek Doubles AI ASIC Target to $2B, Challenges Broadcom in Data Center Custom Silicon
MediaTek doubles its 2026 AI ASIC revenue target to $2B, leveraging Google hyperscaler deals and the NVIDIA RTX Spark chip (featuring MediaTek's N1X Arm CPU). It aims for 10-15% of the $70-80B custom AI chip market by 2027, directly challenging Broadcom's dominance.
Huawei's Tao Law: LogicFolding Bypasses Lithography, 55% Density Gain on Fixed Node
At ISCAS 2026, Huawei's He Tingbo unveiled the Tao Law, replacing geometric scaling with temporal optimization targeting tau (characteristic time). LogicFolding vertically stacks active layers to shorten critical paths, achieving 55% transistor density increase and 41% energy efficiency gain on a fixed node. Kirin 2026 reaches 3.1GHz; Ascend series will adopt LogicFolding. The roadmap projects equivalent 1.4nm density by 2031, fundamentally challenging Moore's Law's lithography dependency.