Reports
AI-generated structured vendor updates
AMD Helios Enters Production: 12-Stack HBM4 Outmuscles NVIDIA, UALoE Opens AI Network
AMD's second-generation Helios rack-scale AI server enters full production, featuring 72 MI455X GPUs with Samsung's exclusive 12-stack HBM4 (31TB per rack). Compared to NVIDIA's 8-stack design, it offers 50% more memory and 30% lower token cost. Microsoft Azure commits to large-scale deployment, solidifying hyperscaler dual-vendor strategy.
AMD launches world's first 2nm GPU MI455X and Zen 6 EPYC, targets NVIDIA and Intel
At Advancing AI 2026, AMD announced 46% data center CPU market share and launched the world's first 2nm GPU, Instinct MI455X, with CDNA architecture and HBM4 memory. The 6th-gen EPYC Venice (Zen 6) was also unveiled, targeting AI workloads.
AMD Helios Rack Challenges NVIDIA NVLink with Open UALoE Interconnect
At Advancing AI 2026, AMD launched the Helios rack with 72 MI455X GPUs, 18 Venice EPYC CPUs, and Pensando networking, claiming 30% higher inference token/$ vs NVIDIA NVL72. It introduced UALoE open interconnect to break NVLink lock-in, partnering with Cerebras, Cisco, and major AI firms.
AMD Helios Full-Stack AI Server Deployed on Azure, UALoE Open Standard Challenges NVLink
AMD and Microsoft Azure announce large-scale deployment of Helios full-stack AI servers, featuring 72 MI455X GPUs, 18 EPYC Venice CPUs, and Pensando DPUs, with 31TB HBM4 and 1.7PB/s memory bandwidth. Two new Azure VM series target Agentic AI and semiconductor design, marking Microsoft's multi-vendor strategy and challenging NVIDIA's dominance.
AMD Invests $5B in Anthropic, Secures 2GW MI450 Deployment, Reshaping AI Compute Ecosystem
AMD and Anthropic announce a strategic partnership: Anthropic will deploy up to 2GW of AMD Instinct MI450 GPUs, with AMD investing up to $5B in Anthropic. They will collaborate on ROCm optimization and Claude workload tuning, marking AMD's transition from chip vendor to AI ecosystem investor and accelerating multi-sourcing in AI compute.
AMD Unveils Zen 6 Venice, MI455X, and Helios Rack-Level Design to Challenge NVIDIA
At Advancing AI 2026, AMD launched Zen 6 EPYC Venice (2nm, up to 256 cores) and MI455X (CDNA5, 432GB HBM4, 40 PFLOPS FP4), along with Helios rack reference design (2.9 exaFLOPS FP4 per rack), claiming a 1000x AI performance roadmap, with major commitments from Meta, OpenAI, and others.
AMD Confirms Zen 6 EPYC Venice: First 2nm Server CPU Launching July 2026
AMD confirms Zen 6 EPYC Venice launch at Advancing AI 2026 (July 22-23). As the first 2nm server CPU, it features triple-core hybrid architecture, up to 192 cores, ~29% single-thread and ~22% multi-thread gains, targeting AI inference and tight CPU-GPU synergy via Infinity Fabric.
AMD Unveils Zen 6/7 CPU and MI400/500 GPU Roadmap, Targets NVIDIA Rubin with HBM4 and 2nm
AMD unveiled its Zen 6/7 CPU and MI400/500 GPU roadmap at its 2026 Financial Analyst Day, featuring TSMC 2nm process and HBM4 memory. The MI400 series boasts 432GB memory, 19.6TB/s bandwidth, and 40 PFLOPs FP4 performance, directly targeting NVIDIA's Vera Rubin architecture with an annual cadence to disrupt the AI hardware monopoly.
AMD MEXT Acquisition Turns NAND Flash into DRAM-Class Memory, Halving AI Inference Cost
AMD acquires MEXT, whose technology makes cheap NAND flash behave like expensive DRAM, doubling to quadrupling usable memory capacity while halving costs. This targets inference and agentic AI memory bottlenecks. AMD also signs a 30MW AI compute deployment deal with Rackspace, rolling out from 2026 to 2028.
AMD Silently Drops TSME from Consumer Ryzen: Security Segmentation Locks Enterprise Users
AMD quietly removed Transparent Secure Memory Encryption (TSME) from consumer Zen 5 Ryzen CPUs, reserving it exclusively for Ryzen PRO series. The change, effective from AGESA 1.2.7.0, is hard to detect on Windows but visible on Linux. This security feature segmentation pushes enterprise buyers toward higher-priced PRO SKUs.
AMD Mustang Peak Threadripper: 144 cores, PCIe 6.0, TR6 socket – Power and memory challenges loom
AMD's Zen 6 Threadripper 'Mustang Peak' is confirmed with 2nm TSMC process, DDR5, PCIe 6.0, and a new TR6 socket. Using Powderhorn CCDs, it scales to 144 cores (288 threads) with clocks above 6 GHz. However, massive power draw and memory bandwidth demands (possibly requiring MRDIMM) raise platform cost concerns.
AMD Ryzen 10000 Series to Swap iGPU for NPU: AI Boost at Cost of Basic Display
Leaks suggest AMD's next-gen Zen 6 desktop CPU 'Olympic Ridge' will replace the integrated GPU with an NPU, targeting >40 TOPS for Copilot+ AI PC certification. It also upgrades the client I/O die to support CUDIMM/CAMM and EXPO 1.2 for faster DDR5. The trade-off boosts local AI but forces nearly all users to rely on a discrete GPU for basic display.
AMD Zen 6 Venice 256-Core EPYC Claims 3.3x Rack Performance Over NVIDIA Vera, But Estimates Raise Questions
AMD unveils first estimated performance of Zen 6 Venice EPYC (2nm, 256 cores), claiming 3.3x rack-level integer throughput over NVIDIA Vera at 100kW total power. A direct counter to NVIDIA's Arm push, but based on projected estimates, not silicon.
NVIDIA's Triple Play: Vera CPU, N1X Laptop Chip, and $6.5B Silicon Photonics Reshape AI Infra Control
NVIDIA delivers first agent-specific Vera CPU (88 Arm v9.2 cores, 1.2TB/s memory bandwidth), teases consumer N1X laptop chip, and invests $6.5B in silicon photonics. This shifts AI orchestration control from x86 to NVIDIA's Arm ecosystem, while CPO addresses memory wall, but volume production remains challenging until post-2028.