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Intel押注3D堆叠AI芯片 18A-PT+Foveros Direct 3D+EMIB-T全栈整合
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AMD Unveils Zen 6/7 CPU and MI400/500 GPU Roadmap, Targets NVIDIA Rubin with HBM4 and 2nm
AMD unveiled its Zen 6/7 CPU and MI400/500 GPU roadmap at its 2026 Financial Analyst Day, featuring TSMC 2nm process and HBM4 memory. The MI400 series boasts 432GB memory, 19.6TB/s bandwidth, and 40 PFLOPs FP4 performance, directly targeting NVIDIA's Vera Rubin architecture with an annual cadence to disrupt the AI hardware monopoly.
Samsung and SK Hynix Announce $300B Investment to Dominate AI Memory and Foundry
Samsung and SK Hynix announce a 10-year, 1,000 trillion won investment plan to expand HBM4 production, improve 3nm GAA yield, and build new AI chip fabs. This aims to cement their HBM duopoly and close the gap with TSMC in advanced foundry, reshaping global AI infrastructure supply chain costs.
Qualcomm HBC Gen 1 Stacks LPDDR to 133 TB/s, Challenging HBM Dominance
Qualcomm announces HBC Gen 1, a 3D-stacked LPDDR memory with integrated compute die, achieving 133 TB/s bandwidth and 6x energy efficiency over HBM. Aimed at replacing HBM in AI accelerators, shipping with AI250 in mid-2027, but supply chain and feasibility remain uncertain.
China's LineShine Tops TOP500: CPU-Only 2.2 ExaFLOPS with ARMv9 and HBM Memory
LineShine supercomputer achieves 2.198 ExaFLOPS FP64 sustained using 13.79 million ARMv9 cores across 20,480 nodes, making it the first system to exceed 2 ExaFLOPS without GPUs. Each node has dual LX2 CPUs (304 cores) with 32GB HBM, demonstrating a CPU+HBM architecture breakthrough for HPC.
MediaTek Lands Exclusive Google TPU v9 Inference Upgrade Triggerfish with 2x SRAM
Google plans a TPU v9 inference upgrade, Triggerfish, exclusively fabbed by MediaTek. It features 2-3x on-chip SRAM, HBM4E DRAM, and a simulation die for local management. Production starts late 2027 with 1-2M units lifecycle, unit price ~30% higher than Humufish.
Google TPU v9 Switches to MediaTek, Breaking Broadcom's AI ASIC Monopoly
Google moves its TPU v9 Humufish design and integration contract from Broadcom to MediaTek, which handles I/O chip design and packaging. Combined with a split-foundry strategy (TSMC N2 compute, Samsung 2nm I/O), this marks a systematic effort to build a multi-vendor, multi-node supply chain, directly dismantling Broadcom's dominance in custom AI ASICs.
Micron-Anthropic Deal: Memory Co-Architecture Locks in AI Supply Chain
Micron and Anthropic sign a strategic agreement covering joint memory/storage architecture design, multi-year supply, Claude adoption, and investment. This ties frontier AI model demands directly to infrastructure design, aiming to optimize token economics and power efficiency, but essentially locks in supply and restructures the ecosystem.
Dell PowerEdge XE8812: Liquid-Cooled Density Trap with NVIDIA Vera Rubin NVL4
Dell launches PowerEdge XE8812 with NVIDIA Vera Rubin NVL4, delivering 144 GPUs per rack, 300kW+ power, and 100% direct liquid cooling. It offers a generational leap in memory and compute density for HPC and AI, but deeply locks users into Dell's PowerRack, iDRAC, and ORv3 ecosystem from chip to rack.
HBM Bottleneck Reshapes AI Infrastructure: Asian Memory Makers Gain Leverage Over Nvidia
SK Hynix, Samsung, and Micron have crossed $1 trillion market cap as HBM becomes the hard limit in AI infrastructure. Asian suppliers now account for 90% of Nvidia's production costs, shifting the bottleneck from GPU compute to stacked memory and advanced packaging.
NVIDIA and SK Hynix Lock Down HBM4/5 Roadmap, Cementing Vera Rubin Supply Chain
NVIDIA and SK Hynix sign a multi-year agreement to co-define HBM4 production and HBM5 pre-research for Vera Rubin GPUs. Samsung also enters HBM4 supply as a second source. The deal elevates SK Hynix from vendor to co-developer, potentially creating a de facto memory standard barrier that marginalizes Micron and others.
HBM Profitability Falls Below DDR5, TrendForce Warns of Multi-Fold Price Surge in 2027
TrendForce reports that HBM per-wafer revenue fell below DDR5 64GB RDIMM in Q1 2026, making HBM less profitable. Suppliers will reallocate capacity, leading to multi-fold HBM4 contract price increases in 2027. Demand from NVIDIA Rubin Ultra and AI ASICs will further tighten supply.
Micron Partners TSMC for Custom HBM4E Logic Dies, Targets 2027 Ramp with 1-gamma DRAM
Micron plans to ramp HBM4E in 2027, transitioning to 1-gamma DRAM and using TSMC for both standard and custom logic dies. This marks a shift from standardized HBM to customized solutions, positioning memory as a strategic asset for AI inference workloads.
Global GPU Shortage to Persist Until 2027: Core Bottleneck for AI Infrastructure Expansion
Global GPU shortage expected to extend to 2027-2028, rooted in AI data center demand surge, constrained HBM production, CoWoS packaging tightness, and geopolitical risks. NVIDIA Rubin's mass production hindered (target reduced from 2M to 1.5M units), with Blackwell capturing 71% of high-end GPU shipments in 2026. Consumer RTX 5080/5070 Ti priced $200-$500 above MSRP, enterprise AI infrastructure procurement cycles will further extend.
NVIDIA Rubin Delayed, Blackwell to Account for 71% of High-End GPU Shipments in 2026
NVIDIA Rubin GPU production target lowered from 2M to 1.5M units due to HBM4 memory validation delays. TrendForce data shows Blackwell share rising from 61% to 71% in 2026, consolidating dominance. Micron exits Rubin HBM4 supply chain, SK hynix to hold 70% share. Analysts maintain overweight ratings, viewing impact as limited. Rubin delay may extend SK hynix's HBM3E market dominance.
NVIDIA Rubin Era: 1.8kW GPU TDP and Mandatory Liquid Cooling Reshape Data Centers
NVIDIA's mandatory liquid cooling is a landmark event in AI infrastructure 'qualitative change' of physical form. When chip power exceeds 1.8kW, air cooling physical limits are breached, the entire data center industry chain—from power architecture, cooling systems to building structure—must be redesigned. This isn't technology upgrade but paradigm shift.
SK Hynix Jumps to TSMC 3nm for HBM4E Logic Die to Counter Samsung's 4nm Lead
SK Hynix plans to use TSMC's 3nm process for the logic die in its 7th-gen HBM4E, a leap from the 12nm used in HBM4. This aims to reverse the performance gap with Samsung (which used 4nm logic in HBM4) and deliver higher bandwidth and power efficiency for next-gen AI chips like NVIDIA's Vera Rubin Ultra.
AMD and Samsung Deepen HBM4 and CXL Memory Technology Collaboration
AMD and Samsung expanded strategic collaboration to co-develop next-gen AI memory solutions, focusing on HBM4 and CXL technologies. The partnership will optimize memory controllers, PHY layers and packaging to enhance AI computing platform performance. Joint efforts will advance HBM4 standardization and explore CXL applications in memory pooling.
AMD and Samsung Deepen Collaboration, Locking HBM4 Supply and Exploring Foundry Partnership
AMD and Samsung signed an MOU, designating Samsung as the primary HBM4 supplier for the next-gen Instinct MI455X GPU and collaborating on DDR5 memory optimized for 6th Gen EPYC CPUs. The companies will also explore opportunities for Samsung to provide foundry services for future AMD products.
Samsung and AMD Deepen AI Hardware Collaboration with HBM4 Supply and Foundry Services
Samsung will be the primary HBM4 supplier for AMD's next-gen MI455X GPU, delivering 13Gbps bandwidth memory. The partners will also develop DDR5 solutions for 6th-gen EPYC CPUs and explore Samsung's foundry services for future AMD products.