Reports
AI-generated structured vendor updates
Nvidia May Cut HBM Capacity Amid Memory Shortage for Rubin Ultra
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Amid Memory Shortage, Nvidia Weighs Cutting HBM4E Capacity for Rubin Ultra GPU
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三星在FMS 2026发布下一代3D内存愿景
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NVIDIA Rubin Ultra GPU HBM shortage test
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Samsung Unveils 400-Layer AI Memory; Shares Rise 2%
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Samsung Unveils Next-Gen 3D-Memory Vision at FMS 2026, Charting the Future of AI Infrastructure
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MediaTek Advances CoWoS, EMIB-T and 3.5D Packaging Strategy
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AMD presentó sus apuestas en servidores, PC y robots para ubicarse en el centro de la revolución de IA
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MediaTek Adopts Dual Packaging: CoWoS and Intel EMIB-T for ASIC
MediaTek CEO confirms ASIC projects adopt Intel EMIB-T packaging alongside TSMC CoWoS. EMIB-T uses micro bridges for high-density interconnects, supporting HBM, achieving 8-10x reticle area at lower cost. Dual-track strategy highlights packaging as a key competitive dimension in AI chips.
Meta launches Meta Compute to sell idle AI capacity, partners with BlackRock on $14B data center
Meta announces Meta Compute, selling idle AI capacity externally, and partners with BlackRock on a $14B data center. Meta is in talks to lease $10B in compute to Anthropic. With 2026 capex raised to $125-145B, Meta transforms from a social platform to an AI infrastructure provider.
TSMC Develops EMIB-Like Packaging with Kinsus to Counter Intel's CoWoS Threat
TSMC, in response to CoWoS capacity constraints and potential customer loss, is developing an EMIB-like advanced packaging technology with Kinsus, aiming to simplify manufacturing steps and reduce costs, preventing clients from shifting to Intel's packaging platform, highlighting the strategic importance of advanced packaging in AI chip competition.
NVIDIA Vera Rubin Goes Global: 10x Token per Megawatt, Locks In AI Factory Standard
NVIDIA announces full production and global delivery of Vera Rubin platform, with CoreWeave and cloud providers deploying NVL72 systems. Featuring Vera CPU and Rubin GPU, the platform delivers 10x token throughput per megawatt over Blackwell, enabling gigawatt-scale AI factories across 350+ sites.
AMD and Schneider Electric Launch Helios Reference Design to Challenge NVIDIA AI Factory
Schneider Electric and AMD jointly announced a reference design for AI data centers based on the AMD Helios rack-scale platform, integrating Instinct GPUs, EPYC CPUs, Pensando networking, and ROCm software. It supports up to 10.4MW capacity and 246kW rack density with liquid cooling removing 84% heat, achieving PUE ~1.12, directly targeting NVIDIA's Vera Rubin solution.
TSMC Develops EMIB-like Packaging to Challenge Intel and Ease CoWoS Bottleneck
TSMC is developing an EMIB-like advanced packaging technology that uses small silicon bridges instead of large silicon interposers, reducing cost and complexity while easing CoWoS capacity constraints. This move counters Intel's EMIB technology and addresses the growing packaging demands of AI accelerators, securing TSMC's dominance in advanced packaging.
Samsung locks 60% capacity in long-term deals, HBM4E sampling, memory shortage through 2028
Samsung Q2 2026 operating profit surged 1814% to 89.5 trillion won, driven by AI memory demand. HBM4E samples delivered, HBM4 revenue to triple QoQ. Samsung locks 60-70% capacity in 5-year LTAs, warns memory shortage through 2028, worsening in 2027.
Intel’s U.S. Advanced Packaging Enables Next-Generation AI Semiconductors - Intel Newsroom
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NVIDIA Rubin GPU Detailed: 3nm Dual-Die, 336B Transistors, 288GB HBM4, NVLink 6 Doubles Bandwidth
NVIDIA unveiled the full Rubin GPU architecture at SIGGRAPH 2026: 3nm dual-die, 336B transistors, 288GB HBM4 with 22 TB/s bandwidth, and NVLink 6 at 3600 GB/s. The NVL72 rack integrates 72 GPUs with 36 Vera CPUs, requiring full liquid cooling due to >1000W TDP.
NVIDIA Vera Rubin NVL72 Enters Production, 10x Energy Efficiency Reshapes AI Infrastructure
NVIDIA has announced full production of the Vera Rubin NVL72 platform, with first shipments to CoreWeave, Microsoft, Amazon, and Oracle. Each rack integrates 72 Rubin GPUs and 36 Vera CPUs, delivering 10x improvement in energy efficiency and inference cost over Blackwell for agentic AI workloads, marking a new era of rack-scale AI infrastructure.
TSMC 2nm Volume Production Begins, AMD First to Launch Venice and MI455X
TSMC has fully ramped its 2nm process at five fabs, contributing ~3% of wafer revenue in Q2. AMD launches the first 2nm-based products: EPYC Venice (256 cores) and Instinct MI455X (320B transistors, 432GB HBM4), shipping in Q3. Samsung targets 1.4nm by 2029, Intel 18A introduces High-NA EUV, intensifying foundry competition.
AMD Launches Helios Rack-Scale AI Platform with MI400 GPUs, Targeting Inference TCO
At Advancing AI 2026, AMD unveiled the Helios rackscale platform integrating 72 MI455X GPUs and 18 EPYC Venice CPUs per rack, delivering 2.9 exaflops FP4 inference and 31TB HBM4 memory. The MI430X offers 288 TFLOPS FP64 for HPC. AMD claims up to 30% more inference tokens per dollar vs. competitors.