Reports
AI-generated structured vendor updates
TSMC Bets on CoPoS and Glass Substrates: Packaging Paradigm Shifts from Wafer-Level to Panel-Level, AI Chip TCO Inflection
TSMC is replacing CoWoS with CoPoS (panel-level packaging), using 750x620mm square panels and glass core substrates, achieving 20-30% unit area cost reduction. Volume production targets 2028, with AMD Zen 7 as first key customer. This fundamentally alters AI chip packaging economics and capacity scaling.
AMD MI430X GPU Delivers >200 TFLOPS Native FP64, Reshaping HPC-AI Convergence Baseline
AMD powers 4 of top 10 TOP500 supercomputers and previews MI430X GPU with >200 TFLOPS native FP64. This targets AI-for-science workloads, making double-precision compute a key metric for converged HPC-AI infrastructure, directly challenging NVIDIA and Intel.
NVIDIA's AI Agents and Digital Twins Reshape Telecom Network Control Plane
At DTW Ignite 2026, NVIDIA showcases its AI agent platform integrating NeMo synthetic data, NemoClaw secure runtime, OpenShell sandbox, and RTX PRO 6000-accelerated digital twins, aiming for autonomous telecom operations. Partners include SoftBank, Amdocs, NTT DATA, etc., moving from task automation to full autonomy.
Arm servers capture >45% data center revenue, x86 ecosystem under AI-driven assault
IDC reports Q1 2026 global server revenue hit a record $122.6B, with Arm-based servers capturing >45% share (x86 at 52%). Accelerated servers (GPU/ASIC/FPGA) generated >70% revenue. Nvidia's Grace CPU (NVL72) and hyperscaler custom Arm chips drive the shift; x86 still leads in unit volume but faces supply constraints.
Qualcomm Launches Dragonfly Datacenter Brand, ARM AI Chips Target Intel, AMD, NVIDIA
Qualcomm announced Dragonfly datacenter brand at Computex 2026, including custom ASICs, standard CPUs, and dedicated AI accelerators, extending computing from edge to cloud. First ASIC shipments moved up to 2026. Analysts project $3B revenue in FY2027. This marks Qualcomm's formal entry into the datacenter, challenging X86 and GPU ecosystems.
TSMC Capacity Crunch Reshapes Foundry Landscape: Google, AMD, Tesla Move to Samsung for Advanced Nodes
TSMC's advanced capacity shortage through 2027 pushes Google, AMD, and Tesla to Samsung for 3nm/2nm foundry services. Samsung's 6.5% market share may see structural growth, shifting global chip supply from single-source to multi-source, though yield and trust issues persist.
AMD MEXT Acquisition Turns NAND Flash into DRAM-Class Memory, Halving AI Inference Cost
AMD acquires MEXT, whose technology makes cheap NAND flash behave like expensive DRAM, doubling to quadrupling usable memory capacity while halving costs. This targets inference and agentic AI memory bottlenecks. AMD also signs a 30MW AI compute deployment deal with Rackspace, rolling out from 2026 to 2028.
AMD Silently Drops TSME from Consumer Ryzen: Security Segmentation Locks Enterprise Users
AMD quietly removed Transparent Secure Memory Encryption (TSME) from consumer Zen 5 Ryzen CPUs, reserving it exclusively for Ryzen PRO series. The change, effective from AGESA 1.2.7.0, is hard to detect on Windows but visible on Linux. This security feature segmentation pushes enterprise buyers toward higher-priced PRO SKUs.
AMD Mustang Peak Threadripper: 144 cores, PCIe 6.0, TR6 socket – Power and memory challenges loom
AMD's Zen 6 Threadripper 'Mustang Peak' is confirmed with 2nm TSMC process, DDR5, PCIe 6.0, and a new TR6 socket. Using Powderhorn CCDs, it scales to 144 cores (288 threads) with clocks above 6 GHz. However, massive power draw and memory bandwidth demands (possibly requiring MRDIMM) raise platform cost concerns.
Qualcomm's RISC-V Gamble: Tenstorrent Acquisition and Edge AI Pivot
Qualcomm pivots from ARM to open-source RISC-V, acquiring Ventana Micro and targeting Tenstorrent for $8-10B. Launches 'Dragonfly' brand for custom AI accelerators, aiming for $35B data-center revenue by 2031, betting on edge AI and AI agents.
AMD MLPerf 6.0: MI350 GPUs Achieve 3.5x Leap with MXFP4, Debut Multi-Node Training
AMD submitted its most comprehensive MLPerf Training 6.0 results, including first multi-node training (FLUX.1 on 512 GPUs) and MXFP4 training recipe. MI355X delivers 3.5x generational leap over MI300X on Llama 2-70B, within 5% of NVIDIA B200. 10 ecosystem partners validated reproducibility.
SiMa.ai Palette Neat: Natural-Language Agentic Environment Dismantles NVIDIA's GPU Moat
SiMa.ai launches open-source Palette Neat, an agentic development environment for Physical AI, paired with its sub-10W Modalix SoM. It uses natural language to abstract compute complexity, slashing dev cycles from months to days. Pin-compatible with NVIDIA SoM, it targets breaking the GPU ecosystem lock-in.
HPE Expands Self-Driving Networks: AI Control Plane Unifies Juniper & Aruba, Locks Management Stack
HPE integrates Juniper networking into its AI Data Center Solution, expanding self-driving networks across edge, campus, DC, and AI factories. New Mist support for CX switches, Marvis AIOps in Aruba Central, and QFX switches optimized for inferencing. Unified SASE platform aims to simplify operations via agentic AI automation, consolidating control under a single AI management plane.
AMD Critical RCE Vulnerability Disclosed After 124 Days, Sparks AI Infrastructure Security Crisis
Security researcher mr.bruh publicly disclosed a critical remote code execution (RCE) vulnerability in AMD processors after 124 days without a fix, with AMD refusing a $10,000 bounty. The flaw affects AI servers running AMD EPYC and Instinct, likened to a Log4j moment for AI infrastructure, forcing enterprises to reassess chip-level security response and supply chain risk.
AMD and Rackspace Deploy 30MW Governed AI Stack: Ecosystem Restructuring from Silicon to Outcomes
AMD and Rackspace sign a definitive agreement to deploy 30MW of AMD AI compute (Instinct GPUs including MI355X, EPYC CPUs) across Rackspace's data centers, creating a governed enterprise AI stack with single accountability from silicon to outcomes, targeting regulated industries.
AMD Ryzen 10000 Series to Swap iGPU for NPU: AI Boost at Cost of Basic Display
Leaks suggest AMD's next-gen Zen 6 desktop CPU 'Olympic Ridge' will replace the integrated GPU with an NPU, targeting >40 TOPS for Copilot+ AI PC certification. It also upgrades the client I/O die to support CUDIMM/CAMM and EXPO 1.2 for faster DDR5. The trade-off boosts local AI but forces nearly all users to rely on a discrete GPU for basic display.
AMD Acquires MEXT: AI-Predicted Flash Nears DRAM Performance to Cut AI Memory TCO
AMD acquires MEXT, an AI-driven memory optimization startup. MEXT's predictive technology makes NAND Flash behave like DRAM, expanding effective memory capacity for AI workloads and lowering TCO. The tech will be integrated across AMD's data center portfolio (EPYC, Instinct) to address memory bottlenecks in large models.
AMD Open-Sources AI Software Stack on Vultr, Taking on NVIDIA CUDA Ecosystem
AMD launches a suite of open-source, modular enterprise AI software components on Vultr Marketplace, including AMD Inference Microservices (AIMs), AI Workbench, Resource Manager, and Solution Blueprints. This aims to provide production-grade AI infrastructure without vendor lock-in, directly challenging NVIDIA's CUDA ecosystem.
NVIDIA Bets on World-Action Models: Control Shifts from VLM to Video Backbones
NVIDIA's blog introduces World-Action Models (WAMs) as a paradigm shift from VLM-based VLAs. WAMs leverage pretrained video/world-model backbones to jointly predict future states and robot actions, aiming to bridge the language-to-action grounding gap. This could redefine robot foundation model training but raises concerns about inference cost and latency.
Google Awards 3M+ TPU Packaging Orders to Intel Foundry, Breaking TSMC's CoWoS Monopoly
Google has awarded Intel Foundry over 3 million units of next-gen TPU advanced packaging orders, leveraging Intel's EMIB technology with production starting in 2028. This marks Intel Foundry's largest external customer win and a pivotal shift in AI chip packaging away from TSMC's CoWoS monopoly.