Reports
AI-generated structured vendor updates
Anthropic Starts Custom AI Chip Development, Talks Samsung 2nm, Aims for Compute Independence
Anthropic has initiated its own AI chip development and is in talks with Samsung for 2nm foundry services. The move aims to reduce reliance on NVIDIA GPUs, optimize inference costs, and strengthen its technology moat ahead of a potential IPO. It joins OpenAI, Google, and others in the custom ASIC race, signaling a shift from software to hardware competition.
AMD Unveils Zen 6/7 CPU and MI400/500 GPU Roadmap, Targets NVIDIA Rubin with HBM4 and 2nm
AMD unveiled its Zen 6/7 CPU and MI400/500 GPU roadmap at its 2026 Financial Analyst Day, featuring TSMC 2nm process and HBM4 memory. The MI400 series boasts 432GB memory, 19.6TB/s bandwidth, and 40 PFLOPs FP4 performance, directly targeting NVIDIA's Vera Rubin architecture with an annual cadence to disrupt the AI hardware monopoly.
Anthropic in talks with Samsung for 2nm AI chip, targeting NVIDIA CUDA control shift
Anthropic is in early talks with Samsung to manufacture custom AI chips using 2nm process and advanced packaging, hiring ex-OpenAI chip engineer Clive Chan. This aims to reduce NVIDIA GPU dependency and seize control of AI infrastructure, signaling a control plane shift in AI compute.
TSMC Hikes Advanced Node Prices 5-10%, Squeezing AI Chip Margins
TSMC informs clients of 5-10% price hikes across all advanced nodes (7nm+), affecting 74% of wafer revenue. Apple, Nvidia, AMD, and others face higher costs, potentially raising AI infrastructure prices.
ASML CEO's EUV Supply Warning Signals a Physical Ceiling on AI Chip Expansion
ASML CEO Fouquet confirms talks with Musk on Terafab but stresses supply constraints. EUV lithography, the sole tool for advanced AI chips, cannot scale quickly. With TSMC, Samsung, Intel, and Musk all vying for limited machines, AI chip capacity allocation becomes a zero-sum game, capping the entire AI infrastructure buildout.
AMD Mustang Peak Threadripper: 144 cores, PCIe 6.0, TR6 socket – Power and memory challenges loom
AMD's Zen 6 Threadripper 'Mustang Peak' is confirmed with 2nm TSMC process, DDR5, PCIe 6.0, and a new TR6 socket. Using Powderhorn CCDs, it scales to 144 cores (288 threads) with clocks above 6 GHz. However, massive power draw and memory bandwidth demands (possibly requiring MRDIMM) raise platform cost concerns.
Applied Materials Launches Deposition and Etch Systems for 3D Chip Scaling
Applied Materials unveils Centris Spectral SiN ALD for uniform dielectric deposition in GAA contacts and Producer Selectra Mo Etch for molybdenum-based 3D NAND word line separation, addressing high-aspect-ratio uniformity issues critical for AI chip manufacturing.
NVIDIA and SK Hynix Lock Down HBM4/5 Roadmap, Cementing Vera Rubin Supply Chain
NVIDIA and SK Hynix sign a multi-year agreement to co-define HBM4 production and HBM5 pre-research for Vera Rubin GPUs. Samsung also enters HBM4 supply as a second source. The deal elevates SK Hynix from vendor to co-developer, potentially creating a de facto memory standard barrier that marginalizes Micron and others.
AMD Zen 6 Venice 256-Core EPYC Claims 3.3x Rack Performance Over NVIDIA Vera, But Estimates Raise Questions
AMD unveils first estimated performance of Zen 6 Venice EPYC (2nm, 256 cores), claiming 3.3x rack-level integer throughput over NVIDIA Vera at 100kW total power. A direct counter to NVIDIA's Arm push, but based on projected estimates, not silicon.
NVIDIA's Triple Play: Vera CPU, N1X Laptop Chip, and $6.5B Silicon Photonics Reshape AI Infra Control
NVIDIA delivers first agent-specific Vera CPU (88 Arm v9.2 cores, 1.2TB/s memory bandwidth), teases consumer N1X laptop chip, and invests $6.5B in silicon photonics. This shifts AI orchestration control from x86 to NVIDIA's Arm ecosystem, while CPO addresses memory wall, but volume production remains challenging until post-2028.
Huawei's Tao Law: LogicFolding Bypasses Lithography, 55% Density Gain on Fixed Node
At ISCAS 2026, Huawei's He Tingbo unveiled the Tao Law, replacing geometric scaling with temporal optimization targeting tau (characteristic time). LogicFolding vertically stacks active layers to shorten critical paths, achieving 55% transistor density increase and 41% energy efficiency gain on a fixed node. Kirin 2026 reaches 3.1GHz; Ascend series will adopt LogicFolding. The roadmap projects equivalent 1.4nm density by 2031, fundamentally challenging Moore's Law's lithography dependency.
Intel CEO: AI Inference Flips CPU/GPU Ratio, Multi-Agent Pushes CPU Back to Core
Intel CEO Lip-Bu Tan forecasts AI inference driving CPU/GPU ratio from 1:8 to 1:1 or even 4:1, with Multi-Agent demands (OS scheduling, KV Cache offload, high-concurrency tool calls) elevating CPU from supporting role to lead. NVIDIA Vera, AMD Venice, and Intel 18A CPU mass production confirm a CPU demand super-cycle.
NVIDIA Vera CPU Threatens x86: 1.5x Performance, 4x Density, Full-Stack AI Lock-In
Rumors indicate NVIDIA will unveil its first general-purpose CPU Vera at Computex 2026, claiming 1.5x x86 performance, 2x throughput, and 4x rack density. Shipment targets: 1.2M units in FY2027, 4.2M in FY2028. Vera targets the AI inference shift from 1:8 to 1:1 CPU/GPU ratio, complementing Grace to create a full GPU+CPU stack.
Meta-Broadcom Multi-Year 2nm AI Chip Partnership, Initial 1GW+ Deployment
Meta and Broadcom announced multi-year, multi-generation strategic partnership to co-develop MTIA (Meta Training and Inference Accelerator) chips through 2029. Initial deployment exceeds 1GW, with multi-gigawatt expansion planned. Industry-first 2nm AI compute accelerator, based on Broadcom XPU platform. Meta has planned MTIA 300/400/450/500 iterations for recommendation, ranking, and large-scale inference. Broadcom CEO Hock Tan to step down from Meta board, transition to strategic advisor.
SK Hynix Jumps to TSMC 3nm for HBM4E Logic Die to Counter Samsung's 4nm Lead
SK Hynix plans to use TSMC's 3nm process for the logic die in its 7th-gen HBM4E, a leap from the 12nm used in HBM4. This aims to reverse the performance gap with Samsung (which used 4nm logic in HBM4) and deliver higher bandwidth and power efficiency for next-gen AI chips like NVIDIA's Vera Rubin Ultra.
TSMC Launches eFoundry Platform to Enhance Semiconductor Design Collaboration
TSMC introduces eFoundry online portal integrating design tools, IP resources, and process technology files to enhance collaboration efficiency with design customers. The platform supports advanced process design challenges through digital tools, accelerating product development from design to mass production.
TSMC Launches Mask Service to Strengthen One-Stop Chip Manufacturing
TSMC officially launches mask manufacturing service covering full process from data preparation to inspection and repair. The service integrates mask fabrication capabilities for process co-optimization and faster time-to-market. This strengthens TSMC's one-stop manufacturing solution and deepens customer collaboration.
NVIDIA and SK hynix Co-Architect Next-Gen Memory for AI Factories, Locking HBM4 to Vera Rubin
NVIDIA and SK hynix announce a multi-year tech partnership to co-develop next-gen memory for Vera Rubin, RTX Spark, and Jetson Thor. Separately, SK Telecom deploys a gigawatt-scale AI cloud using the full DGX stack, targeting 2027. This elevates SK hynix from supplier to co-architect, strengthening NVIDIA's lock-in on HBM and the AI ecosystem.