Reports
AI-generated structured vendor updates
Meta Shifts MTIA ASIC to Samsung 2nm: Ecosystem Restructuring in AI Chip Fab
Meta partners with Samsung for next-gen MTIA ASIC production, moving from TSMC to Samsung 2nm node. Targeting hundreds of thousands of units to support 5GW data center goal by 2030, with new chip every six months, restructuring the AI chip supply chain ecosystem.
Anthropic in talks with Samsung for 2nm AI chip, targeting NVIDIA CUDA control shift
Anthropic is in early talks with Samsung to manufacture custom AI chips using 2nm process and advanced packaging, hiring ex-OpenAI chip engineer Clive Chan. This aims to reduce NVIDIA GPU dependency and seize control of AI infrastructure, signaling a control plane shift in AI compute.
Google TPU v9 Switches to MediaTek, Breaking Broadcom's AI ASIC Monopoly
Google moves its TPU v9 Humufish design and integration contract from Broadcom to MediaTek, which handles I/O chip design and packaging. Combined with a split-foundry strategy (TSMC N2 compute, Samsung 2nm I/O), this marks a systematic effort to build a multi-vendor, multi-node supply chain, directly dismantling Broadcom's dominance in custom AI ASICs.
TSMC under triple pressure: customer diversification, patent challenges, and EUV strategy shift
TSMC faces operational, legal, and commercial pressures: Google splits Icefish AI chip production with Samsung, US ITC patent probe risks import bans, and resource bottlenecks (labor, water, power) limit expansion. TSMC confirms it will skip high-NA EUV until 2029, using multi-patterning on low-NA EUV for 2nm, saving $5-10B.
ASML EXE:5200 High-NA EUV: 8nm Resolution Locks 2nm Node, Cost Trap Looms
ASML launches the EXE:5200 High-NA EUV lithography system, boosting resolution from 13nm to 8nm and wafer throughput to 220 WPH, enabling 2nm and beyond. Intel is the first customer for its 18A process. ASML also reveals Hyper-NA (NA 0.85) development for sub-1nm nodes.
Samsung 3nm GAA Yield Hits 80%, Lands Nvidia Order: TSMC Monopoly Challenged
Samsung Electronics announced its 3nm GAA process yield has exceeded 80%, securing orders from Nvidia for mid-range GPUs. This milestone marks the commercialization of Samsung's SF3 technology, aiming to reduce Nvidia's reliance on TSMC.
TSMC Discloses 2nm and Beyond Technology Roadmap
TSMC announces its 2nm (N2) process will adopt GAAFET architecture replacing FinFET, with plans for subsequent A-series nodes. The technology targets performance and efficiency gains for HPC and mobile applications, leveraging new materials and 3D packaging for AI and 5G/6G demands.
TSMC Releases Advanced Process Roadmap, N2 and A16 Technologies Lead Chip Innovation
TSMC unveiled its logic process technology roadmap, highlighting advanced nodes like N2 and A16. N2 adopts GAAFET architecture for performance and power efficiency gains, while A16 integrates backside power delivery for HPC optimization, reinforcing TSMC's leadership in semiconductor manufacturing.