Reports
AI-generated structured vendor updates
Intel's 18A Xeon 6+ and Rack Scale AI: A CPU-Centric Challenge to NVIDIA's Inference Empire
At Computex 2026, Intel launched the 18A-node Xeon 6+ processor, the Rack Scale AI platform with SambaNova's SN-50 RDU, and a fully disaggregated inference service (Vector Core Compute). This CPU-centric hybrid architecture targets agentic AI inference workloads, directly challenging NVIDIA's Vera Rubin NVL72 and GPU-dominated ecosystem.
NVIDIA RTX Spark and Nemotron-3 Ultra: AI Control Shifts from Cloud to Personal Edge
NVIDIA launched RTX Spark personal AI supercomputer (co-developed with MediaTek) and Nemotron-3 Ultra open-source model at GTC Taipei 2026. The N1X chip delivers 1 PFLOPS local AI compute, bringing LLM inference to PCs. This marks NVIDIA's pivot from cloud GPU vendor to edge AI infrastructure monopolist, redefining the PC as an AI-native device.
OpenAI and Broadcom Launch Jalapeño ASIC for LLM Inference, 9-Month Tapeout
OpenAI and Broadcom unveil Jalapeño, a custom ASIC for LLM inference, achieving tapeout in 9 months. The chip reduces data movement and claims superior performance per watt. Deployment planned by end of 2026, marking OpenAI's shift to integrated hardware-software infrastructure.
ReflectionAI Secures $6.3B SpaceX Compute Deal, Open-Source AI Breaks Hardware Lock-in
Open-source AI startup ReflectionAI signs a $6.3B deal with SpaceXAI to lease NVIDIA GB300 compute at Colossus 2 for training open-weight frontier models. This gives open-source labs parity with closed-source giants but creates deep dependency on NVIDIA's proprietary hardware.
US Orders Anthropic to Globally Shutdown Fable 5 and Mythos 5: AI Export Control Escalates
On June 22, 2026, the US government ordered Anthropic to globally shut down its most advanced models, Fable 5 and Mythos 5, citing their autonomous cyberattack capability (ExploitBench 78.0%). This extends export controls from hardware to model weights, marking a new era of sovereign AI governance.
Coherent Expands InP Fab with $50M CHIPS Grant, AI's Connectivity Bottleneck Drives Photonics Arms Race
Coherent receives $50M CHIPS Act grant to expand its 6-inch InP fab in Texas, quadrupling capacity. NVIDIA's $2B strategic investment and CEO Jensen Huang's presence signal a shift from GPU compute scaling to optical interconnect as the new AI infrastructure bottleneck.
NVIDIA Acquires Groq LPU: Inference Architecture Shift from HBM to On-Chip SRAM
NVIDIA signs ~$20B licensing deal with Groq for LPU tech, featuring 230MB on-chip SRAM at 80TB/s bandwidth. This targets Transformer inference decode, replacing HBM bottlenecks with ultra-low latency on-chip storage, potentially reshaping the AI inference chip landscape.
NVIDIA Tops Data Center Ethernet Market: GPU Compute Dictates Network Architecture
IDC reports NVIDIA captured 21.5% of the data center Ethernet switch market in Q1 2026, with $2.1B revenue. This milestone, driven by the Spectrum-X platform using RoCE and NVLink, marks a control shift where GPU compute dictates network architecture, directly challenging Cisco and Arista.
Huawei Ascend 910C Trains 1.6T-Parameter MoE Model: First Full Pipeline on Domestic AI Chips
Huawei, in collaboration with research institutes, completed full-parameter post-training of DeepSeek-V4-Pro (1.6 trillion parameters, MoE) on an Ascend 910C cluster. Key metrics: stable 1,500 steps on 1,000 cards, 30% compute utilization, 14% operator efficiency gain, zero reliance on foreign GPUs. This marks the first end-to-end trillion-parameter training loop on domestic chips.
SK Hynix HBM4E Samples: 3nm Logic, 384GB/GPU, Igniting AI Memory Bandwidth Arms Race
SK Hynix has sampled its 12-layer HBM4E, featuring TSMC 3nm logic die and enhanced per-pin bandwidth, targeting Nvidia Rubin Ultra with 384GB per GPU. This marks the start of a sprint with Samsung in next-gen AI memory, where HBM BOM share has surged to 65-70%.
NVIDIA Absorbs Groq LPU: Feynman GPU to Integrate SRAM Inference Tile, Hybrid Architecture by 2028
NVIDIA secures Groq's LPU inference technology via a non-exclusive license and key hires, planning to integrate large SRAM tiles into its 2028 Feynman GPU using TSMC SoIC hybrid bonding. This enables deterministic scheduling and 80TB/s on-chip bandwidth, shifting NVIDIA from a pure GPU vendor to a hybrid inference/training platform.
Intel Lands Google TPU Package Order: Foundry Pivot Gains Traction, TSMC Still Core
Intel secured a multi-million unit order for Google TPU packaging using its EMIB-T technology, marking its largest external AI chip deal. However, analysts caution the order is primarily for packaging, not wafer fabrication, with TSMC retaining the core manufacturing role.