Reports
AI-generated structured vendor updates
Meta Invests $9.17B in Canada AI Data Center, Iris AI Chip Mass Production Begins MTIA Roadmap
Meta announced a $9.17B AI data center in Canada with 1GW capacity, and its first in-house AI chip Iris will mass produce in September, kicking off the MTIA four-generation roadmap. Meta targets 14GW compute by 2027, using 6-month chip iterations to challenge NVIDIA's annual cadence and reduce GPU dependency.
AWS boosts Trainium 3 shipments, accelerating ASIC substitution for NVIDIA GPUs
Supply chain sources indicate Amazon AWS has instructed vendors to increase Trainium 3 shipments for Q3 2026 by 20-30%. This signals strong confidence in its custom ASIC strategy to reduce dependence on NVIDIA GPUs, leveraging superior cost and power efficiency for cloud AI training.
Anthropic Starts Custom AI Chip Development, Talks Samsung 2nm, Aims for Compute Independence
Anthropic has initiated its own AI chip development and is in talks with Samsung for 2nm foundry services. The move aims to reduce reliance on NVIDIA GPUs, optimize inference costs, and strengthen its technology moat ahead of a potential IPO. It joins OpenAI, Google, and others in the custom ASIC race, signaling a shift from software to hardware competition.
Anthropic Launches Custom AI Chip: Vertical Integration to Control Inference Cost and Supply
Anthropic launched Claude Sonnet 5 and revealed a custom AI chip initiative, using Samsung foundry. This move aims to reduce dependency on NVIDIA, control long-term inference costs, and marks Anthropic's shift from a pure software company to a vertically integrated infrastructure firm.
Anthropic in talks with Samsung for 2nm AI chip, targeting NVIDIA CUDA control shift
Anthropic is in early talks with Samsung to manufacture custom AI chips using 2nm process and advanced packaging, hiring ex-OpenAI chip engineer Clive Chan. This aims to reduce NVIDIA GPU dependency and seize control of AI infrastructure, signaling a control plane shift in AI compute.
OpenAI and Broadcom Tape Out First Inference ASIC Jalapeño in 9 Months, Targeting NVIDIA Dominance
OpenAI and Broadcom unveil Jalapeño, their first custom inference ASIC, fabricated on TSMC 3nm and optimized for Transformer models. Targeting a 50% inference cost reduction, it taped out in 9 months and is slated for deployment in gigawatt-scale data centers by late 2026, marking OpenAI's strategic pivot to full-stack AI infrastructure and a direct challenge to NVIDIA's inference hegemony.
Arm AGI CPU Demand Doubles, Targets AI Inference Control, Threatens x86 Dominance
Arm doubled its demand forecast for its first in-house datacenter CPU, the AGI CPU, projecting over $2B revenue in FY2027-2028. The 136-core, 3nm Neoverse V3-based chip targets agentic AI inference, claiming 2x rack-level performance over x86. Meta is a key partner; OpenAI, Cloudflare also onboard. This marks Arm's strategic pivot from IP licensor to direct silicon vendor.
Arm Doubles AGI CPU Revenue Target, Signaling Pivot from IP Licensor to Direct Silicon Competitor
Arm reported record FY2026 revenue of $4.92B and doubled its AGI CPU revenue forecast to over $2B by 2028. The 136-core, 3nm, 300W processor, co-developed with Meta, targets AI Agent workloads and has attracted OpenAI and major hyperscalers. This marks Arm's strategic shift from IP licensing to direct silicon competition, triggering FTC antitrust scrutiny.
AWS AI Annual Revenue Exceeds $15B, Self-developed Chips Double to $20B
Amazon CEO Andy Jassy disclosed AWS AI service scale for the first time, accounting for about 10% of AWS $142B annualized revenue. Self-developed chips (Graviton, Trainium, Nitro) annualized revenue exceeded $20B (doubled QoQ); 2026 capex expected at $200B; analysts predict AWS could reach $600B annual sales.
Apple Launches M5 Chip Family with Enhanced AI Performance and Storage
Apple introduces M5 series chips with 4x AI performance boost, MacBook Pro standard storage increased to 1TB-2TB, and Wi-Fi 7 support. Launches entry-level MacBook Neo with fanless design and custom chips, expanding low-price market.
Google Launches Mid-Range Pixel 10a with Enhanced AI Photography and Durability
Google launched the Pixel 10a smartphone, featuring its Tensor G4 chip and AI photography tools, focused on durability and mid-market positioning. This continues Google's strategy of integrating hardware and AI for differentiation, without enterprise-level architectural changes.
Huawei Releases AI-Native Data Center Networking Solution Galaxy AI Fabric 2.0
Huawei launched Galaxy AI Fabric 2.0 data center networking solution with AI-Native architecture for autonomous networking. It includes self-developed Solar 5.0 chip switches, iLossless 3.0 algorithm, and intelligent management platform, supporting 10,000-card AI clusters.
Apple Launches Entry-Level MacBook Neo to Strengthen On-Device AI Deployment
Apple introduces the $599 MacBook Neo with its A18 Pro chip, claiming 3x faster on-device AI processing than x86 PCs. The device integrates Apple Intelligence and macOS Tahoe, representing Apple's strategy to expand into mainstream pricing with custom silicon.
Apple Enhances App Store Developer Tools and Privacy Labels
Apple updated its App Store platform with enhanced Xcode Cloud CI/CD service and new App Store Connect API for developer automation. Introduced more detailed app privacy labels for data collection disclosure. UI optimizations and improved recommendation algorithms enhance app discovery.
AWS Launches Inferentia2 Chip for Generative AI Infrastructure Optimization
AWS launched second-gen Inferentia2 AI inference chip, designed for Transformer models with 4x performance boost and support for 175B parameter models. Integrated into EC2 Inf2 instances with UltraClusters architecture for large-scale deployment, offering 40% better cost-performance and 50% lower power consumption than GPU instances.
NVIDIA Acquires Groq LPU: Inference Architecture Shift from HBM to On-Chip SRAM
NVIDIA signs ~$20B licensing deal with Groq for LPU tech, featuring 230MB on-chip SRAM at 80TB/s bandwidth. This targets Transformer inference decode, replacing HBM bottlenecks with ultra-low latency on-chip storage, potentially reshaping the AI inference chip landscape.