Reports
AI-generated structured vendor updates
AMD Unveils Zen 6 Venice, MI455X, and Helios Rack-Level Design to Challenge NVIDIA
At Advancing AI 2026, AMD launched Zen 6 EPYC Venice (2nm, up to 256 cores) and MI455X (CDNA5, 432GB HBM4, 40 PFLOPS FP4), along with Helios rack reference design (2.9 exaFLOPS FP4 per rack), claiming a 1000x AI performance roadmap, with major commitments from Meta, OpenAI, and others.
华为昇腾950超节点亮相WAIC 2026，单柜64卡支持8192卡高速互联
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Huawei Ascend 950 Supernode: Self-Developed HCCS Interconnect for Sovereign AI Compute Ecosystem
Huawei unveiled the Ascend 950 Supernode at WAIC, integrating 32 self-developed Ascend 950 AI processors with HCCS high-speed interconnect, achieving 2.5x compute density and supporting trillion-parameter model training, offering a sovereign AI compute alternative free from overseas supply chains.
Huawei unveils Atlas 950 SuperPoD: 1024-card memory-coherent AI supernode
Huawei unveiled the Atlas 950 SuperPoD at WAIC 2026, powered by the 950DT chip, supporting 1024 interconnected cards with 256TB unified memory addressing. Designed for trillion-parameter model training and Agentic AI inference, it marks a shift from chip-level stacking to system-level unified architecture.
Huawei Ascend 950 SuperPoD: 1024 NPUs with 256TB Unified Memory Redefines AI Compute
Huawei unveiled the Ascend 950 SuperPoD at WAIC 2026, featuring 1024 NPUs per cabinet with 256TB unified memory and 3μs latency. This system-level innovation compensates for process limitations, scaling to 500,000 NPUs for trillion-parameter model training, shifting the compute race from single-chip to system efficiency.
Huawei's Tao Law: LogicFolding Bypasses Lithography, 55% Density Gain on Fixed Node
At ISCAS 2026, Huawei's He Tingbo unveiled the Tao Law, replacing geometric scaling with temporal optimization targeting tau (characteristic time). LogicFolding vertically stacks active layers to shorten critical paths, achieving 55% transistor density increase and 41% energy efficiency gain on a fixed node. Kirin 2026 reaches 3.1GHz; Ascend series will adopt LogicFolding. The roadmap projects equivalent 1.4nm density by 2031, fundamentally challenging Moore's Law's lithography dependency.
Huawei Ascend 910C Trains 1.6T-Parameter MoE Model: First Full Pipeline on Domestic AI Chips
Huawei, in collaboration with research institutes, completed full-parameter post-training of DeepSeek-V4-Pro (1.6 trillion parameters, MoE) on an Ascend 910C cluster. Key metrics: stable 1,500 steps on 1,000 cards, 30% compute utilization, 14% operator efficiency gain, zero reliance on foreign GPUs. This marks the first end-to-end trillion-parameter training loop on domestic chips.