Reports
AI-generated structured vendor updates
TSMC Launches eFoundry Platform to Enhance Semiconductor Design Collaboration
TSMC introduces eFoundry online portal integrating design tools, IP resources, and process technology files to enhance collaboration efficiency with design customers. The platform supports advanced process design challenges through digital tools, accelerating product development from design to mass production.
TSMC Launches Mask Service to Strengthen One-Stop Chip Manufacturing
TSMC officially launches mask manufacturing service covering full process from data preparation to inspection and repair. The service integrates mask fabrication capabilities for process co-optimization and faster time-to-market. This strengthens TSMC's one-stop manufacturing solution and deepens customer collaboration.
TSMC Shifts to System-Level Foundry Services via Technology Platform Strategy
TSMC introduces a technology platform strategy combining advanced processes and 3D packaging to deliver customized semiconductor solutions for mobile, HPC, automotive, and IoT. This marks a shift from pure-play foundry to system-level solutions, enhancing customer lock-in and service barriers through vertical integration.
TSMC Launches Specialty Technology Platform for Diverse Applications
TSMC introduces a specialty technology platform integrating mature and specialty processes like BCD, HV, and CIS to provide customized semiconductor solutions for automotive, IoT, RF, and analog/power management applications. The platform addresses specific requirements for performance, reliability, and power efficiency across diverse use cases.
TSMC Releases Advanced Process Roadmap, N2 and A16 Technologies Lead Chip Innovation
TSMC unveiled its logic process technology roadmap, highlighting advanced nodes like N2 and A16. N2 adopts GAAFET architecture for performance and power efficiency gains, while A16 integrates backside power delivery for HPC optimization, reinforcing TSMC's leadership in semiconductor manufacturing.
TSMC Launches Advanced Packaging Platform for Heterogeneous Integration
TSMC launches an advanced packaging platform integrating CoWoS, InFO, and SoIC 3D stacking technologies for micron-level vertical integration of chips across process nodes. It delivers higher interconnect density, bandwidth, and lower power consumption, supporting complex SoC designs as part of its Open Innovation Platform to accelerate time-to-market.
TSMC Launches Open Innovation Platform to Enhance Chip Design-Manufacturing Collaboration
TSMC introduces Open Innovation Platform® integrating process technology, IP portfolio, design tools and manufacturing expertise to provide a unified collaborative environment for chip design and manufacturing. The platform utilizes silicon-validated IP, advanced PDKs and optimized EDA flows to reduce time-to-market and improve first-time silicon success rates.
ASML Integrates Lithography and Metrology Systems in Semiconductor Manufacturing Ecosystem
ASML has built an integrated product matrix centered on lithography systems, combined with metrology and computational lithography. Its EUV and DUV scanners support advanced chip manufacturing, while YieldStar metrology and Tachyon software enable process optimization and yield control. This forms a complete semiconductor manufacturing toolchain from patterning to process control.
ASML Technology Overview: The Core of Semiconductor Manufacturing from Lithography to Metrology
ASML, a global leader in semiconductor equipment, centers its technology portfolio around the core process of lithography. This brief highlights its three key technological pillars: Lithography, Metrology & Inspection, and Computational Lithography. In lithography, ASML offers a full range from Deep Ultraviolet (DUV) to Extreme Ultraviolet (EUV) solutions. Its EUV lithography machines, utilizing 13.5-nanometer wavelength light, are critical for manufacturing advanced logic and memory chips. The technology generates plasma light by firing a high-power laser at tin droplets, coupled with precision optics and vacuum systems for nanoscale patterning. For metrology and inspection, ASML employs tools like HMI e-beam metrology to perform nanoscale inspection of post-lithography wafers for pattern fidelity, overlay accuracy, and defects, providing essential data for process control. Computational lithography, via the Tachyon software platform, uses complex algorithms and massive computing power to model and optimize between chip design (mask) and physical manufacturing. This compensates for physical effects during lithography to ensure final wafer pattern accuracy. These three technologies work in close synergy, forming a complete technological loop from design to manufacturing.
Apple Launches iPhone 17e: Doubles Performance with In-House C1X Modem, Holds $599 Starting Price
Apple launched the iPhone 17e, featuring its in-house C1X cellular modem, which doubles the speed and improves energy efficiency by 30% compared to its predecessor. The model also includes the A19 chip and doubles the base storage to 256GB while maintaining the same starting price, aiming to strengthen its competitiveness in the premium entry-level segment.
Apple and Hermès Collaborate Again, Unveil New Apple Watch Hermès Collection
Apple has once again partnered with luxury brand Hermès to launch a new Apple Watch Hermès collection. This series represents a continuation of their long-term collaboration, aiming to fuse Apple's smart technology with Hermès' craftsmanship and design aesthetics. The new product line includes several exclusive watch bands and faces. For bands, it introduces a new Single Tour band in Swift leather, a redesigned Double Tour band with more color options, and a new Toile H printed band inspired by Hermès' signature canvas material. These are paired with two new exclusive watch faces: the "Toile H" face combines dynamic printed patterns with functional complications, while the "Hermès Circumference" face features elegant numeral typography and a radial minute track. The collection will be available via Apple's website, Apple Store retail locations, and select Hermès boutiques. **Comment**: This collaboration is a classic example of the fusion between technology and luxury, enhancing product value and brand premium through exclusive designs and material upgrades. It primarily targets high-end consumers seeking a blend of fashion and technology. For Apple, this helps solidify its position in the premium wearable market and expand into new customer segments.
Ericsson and Intel Collaborate on AI-Native 6G Network Architecture
Ericsson and Intel announced deepened collaboration to advance AI-native 6G from research to commercialization. The partnership integrates wireless access network, packet core, and cloud RAN technologies with focus on AI-driven architecture. It aims to create open and efficient 6G development path using Intel Xeon processors and advanced process nodes.
TSMC Strengthens Chip Design Ecosystem via IP Alliance
TSMC's IP Alliance under its Open Innovation Platform integrates certified third-party silicon IP providers, ensuring interoperability and PPA optimization on advanced processes. This reduces design risks, accelerates time-to-market, and strengthens its manufacturing platform appeal.
TSMC Announces Agile Intelligent Operations Strategy for Smart Manufacturing
TSMC launches an Agile Intelligent Operations strategy integrating AI analytics and automation for predictive maintenance and real-time production optimization. The strategy builds a smart manufacturing ecosystem to enhance supply chain collaboration and operational flexibility.
ASML Advances Lithography Paradigm Shift Through Computational Patterning
ASML integrates EUV lithography with computational patterning techniques (OPC, SMO, Multi-Beam) to systematically optimize imaging chains and push k1 factor beyond physical limits. This represents a paradigm shift from hardware-driven advances to hardware-algorithm fusion, enabling more economical chip scaling.
ASML Discloses Core Precision Mechatronics Technology in Lithography Systems
ASML detailed the precision mechatronics foundation of its lithography systems, including ultra-precision motion control platforms, active vibration isolation, and advanced sensor feedback loops. These technologies enable nanometer-scale chip manufacturing accuracy and highlight critical system-level engineering capabilities.
ASML Details EUV Lithography Light Source Technology Evolution
ASML published a technical article detailing the evolution of lithography light sources from mercury lamps to excimer lasers and EUV technology. EUV uses 13.5nm wavelength light generated by laser-pulsed tin droplets, enabling finer circuit patterns for sub-7nm semiconductor manufacturing.
ASML Explores Lithography Core Technology Path and Physical Limits
ASML details the core physical principle of lithography—Rayleigh criterion—revealing the resolution formula and optimization paths. Through EUV light sources, high-NA lenses, and computational lithography, it continuously pushes chip manufacturing limits.
ASML Details Lithography Principles and Process Evolution
ASML released a technical article detailing lithography fundamentals and evolution path, focusing on technological development from optics to EUV, highlighting resolution enhancement techniques and system integration trends.
Unveiling Chip Manufacturing: A Technical Breakdown from Wafer to Microchip
Brief: ASML released a technical article detailing the entire manufacturing process of microchips. The process begins with ultra-pure silicon wafers, where circuit patterns are transferred onto the wafer through lithography—the most critical step. The article emphasizes the role of lithography machines, which use Deep Ultraviolet (DUV) or Extreme Ultraviolet (EUV) light sources to precisely project design patterns from a mask onto a photoresist-coated wafer via complex optical systems. This is followed by hundreds of steps including etching, ion implantation, deposition, chemical mechanical planarization (CMP), and metal interconnection, ultimately forming hundreds of individual chips on a single wafer before final testing, dicing, and packaging. The entire manufacturing process takes place in cleanrooms, demanding extreme precision and cleanliness, involving nanoscale dimension control. The article highlights EUV lithography as the key enabling technology for the most advanced nodes (e.g., 5nm and below), with its 13.5nm wavelength light source enabling finer circuit patterns. **Comment**: This content is not a new product launch but a科普-style technical explanation of the core manufacturing process, particularly the "bottleneck" step of lithography. It is valuable for readers seeking to understand the foundational technologies of the semiconductor industry and ASML's core business value, underscoring the irreplaceable role of lithography, especially EUV technology, in advanced process nodes.