Reports
AI-generated structured vendor updates
Intel押注3D堆叠AI芯片 18A-PT+Foveros Direct 3D+EMIB-T全栈整合
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Samsung GAIA AI PC Chip Samples with Memory-Centric NPU, Targeting 50 TOPS
Samsung launches GAIA AI PC processor with 4nm process and memory-centric NPU, integrating LPDDR5X controller with NPU for near-memory computing, achieving 40% energy efficiency improvement and 50 TOPS. Certified for Microsoft Copilot+ PC, Lenovo to adopt in Q4 2026.
NVIDIA Rigel Core: Single-Threaded CPU as the New Control Plane for Agentic AI
NVIDIA unveils Rosa CPU architecture with custom Rigel core (Arm v9.2), targeting single-threaded performance for Agentic AI workloads, paired with Feynman GPU (1.6nm, 50 PFLOPS) in 2028. This shifts CPU design from core-count scaling to serial-latency optimization, directly challenging AMD EPYC and Intel Xeon dominance.
MediaTek and Alibaba Cloud Deploy Tongyi Qianwen LLM on Dimensity Chips
MediaTek partners with Alibaba Cloud to deploy a small version of the Tongyi Qianwen LLM on Dimensity 9300/8300 mobile platforms, enabling offline multi-turn conversations. This move aims to capture edge AI inference control via NPU optimization and SDK integration, directly challenging Qualcomm.
NVIDIA Denies Kyber NVL144 Delay, But 78-Layer PCB Bottleneck Exposes AI Hardware Physics Limit
NVIDIA officially denies reports of Kyber NVL144 rack delay to 2028, but SemiAnalysis revelations about a 78-layer ultra-high-density PCB midplane bottleneck and Rubin Ultra cancellation expose hard physical limits in signal integrity and manufacturing, opening a strategic window for AMD and Google.
NVIDIA Kyber NVL144 Delayed to 2028: Midplane PCB Manufacturing Becomes AI Scaling Bottleneck
SemiAnalysis reveals NVIDIA's Kyber NVL144 delayed beyond 12 months to 2028 due to 78-layer Orthogonal Backplane manufacturing challenges. The interim NVL72x2 solution is cancelled due to operational burdens, and the 4-die Rubin Ultra is also scrapped, leaving a product gap in NVIDIA's scaling roadmap.
Anthropic Starts Custom AI Chip Development, Talks Samsung 2nm, Aims for Compute Independence
Anthropic has initiated its own AI chip development and is in talks with Samsung for 2nm foundry services. The move aims to reduce reliance on NVIDIA GPUs, optimize inference costs, and strengthen its technology moat ahead of a potential IPO. It joins OpenAI, Google, and others in the custom ASIC race, signaling a shift from software to hardware competition.
AMD Unveils Zen 6/7 CPU and MI400/500 GPU Roadmap, Targets NVIDIA Rubin with HBM4 and 2nm
AMD unveiled its Zen 6/7 CPU and MI400/500 GPU roadmap at its 2026 Financial Analyst Day, featuring TSMC 2nm process and HBM4 memory. The MI400 series boasts 432GB memory, 19.6TB/s bandwidth, and 40 PFLOPs FP4 performance, directly targeting NVIDIA's Vera Rubin architecture with an annual cadence to disrupt the AI hardware monopoly.
NVIDIA Vera Rubin AI Platform Slated for July 2026 Shipments, Iterative Compute Upgrade
NVIDIA confirms its next-gen AI compute platform, Vera Rubin, will start shipping in July 2026 to major cloud providers like Microsoft and Google. The platform uses an advanced process node to boost AI training and inference performance, representing an iterative upgrade over Hopper and Blackwell without a fundamental architectural shift.
英伟达RTX 5080公版显卡将在BW2026限量发售，售价8299元
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Meta Shifts MTIA ASIC to Samsung 2nm: Ecosystem Restructuring in AI Chip Fab
Meta partners with Samsung for next-gen MTIA ASIC production, moving from TSMC to Samsung 2nm node. Targeting hundreds of thousands of units to support 5GW data center goal by 2030, with new chip every six months, restructuring the AI chip supply chain ecosystem.
Anthropic in talks with Samsung for 2nm AI chip, targeting NVIDIA CUDA control shift
Anthropic is in early talks with Samsung to manufacture custom AI chips using 2nm process and advanced packaging, hiring ex-OpenAI chip engineer Clive Chan. This aims to reduce NVIDIA GPU dependency and seize control of AI infrastructure, signaling a control plane shift in AI compute.
Samsung Restarts 1.4nm Foundry Node, Pre-emptively Locks Equipment Supply Chain
Samsung Electronics restarts 1.4nm (SF1.4) process commercialization, ordering equipment vendors to develop tools early. The node will use High-NA EUV lithography and GAA transistors, fabbed at NRD-K campus. This move aims to catch up with TSMC and Intel, but mass production timeline remains undisclosed.
Etched Unveils Sohu Transformer ASIC: Claims 20x H100 Inference Throughput, Challenging NVIDIA's Grip
AI chip startup Etched emerges from stealth with Sohu, a Transformer-specific ASIC on TSMC N4P with 144GB HBM3E. By hardwiring attention mechanisms, it claims 20x throughput and 140x price-performance vs. H100 on Llama 70B. With $800M total funding and first racks shipping this summer, it directly challenges NVIDIA's inference dominance.
Samsung Re-accelerates 1.4nm Node R&D, Adopts High-NA EUV Lithography
Samsung Electronics is re-accelerating its 1.4nm (SF1.4) process node R&D, targeting mass production by 2028-2029. It has procured High-NA EUV lithography equipment from ASML for its NRD-K R&D complex and ordered tools for 12th-gen V-NAND with wafer stacking. The move aims to catch up with TSMC and Intel in the AI chip foundry race.
TSMC, ASML, imec Demonstrate 300mm 2D Material CMOS with 50nm CPP, 94% Yield
TSMC, ASML, and imec jointly demonstrated the first 300mm wafer-scale integration of 2D material transistors at VLSI 2026, achieving 50nm contacted poly pitch (CPP) for MoS₂ nFET and WS₂/WSe₂ pFET with 28nm channel length and 94% yield, marking a critical step toward industrializing 2D semiconductors.
TSMC Adds Winbond to WoW 3D Stacking Memory Supply, Breaking DRAM Oligopoly
Winbond joins TSMC's Wafer-on-Wafer (WoW) 3D stacking advanced packaging supply chain, becoming a new DRAM wafer supplier alongside Samsung, SK Hynix, and Micron. This move reduces reliance on the three global DRAM giants and strengthens AI chip packaging supply resilience. Winbond provides DRAM wafers for vertical stacking with TSMC logic wafers, offering 8GB capacity and 256GB/s bandwidth via its CUBE solution.
Samsung and SK Hynix Announce $300B Investment to Dominate AI Memory and Foundry
Samsung and SK Hynix announce a 10-year, 1,000 trillion won investment plan to expand HBM4 production, improve 3nm GAA yield, and build new AI chip fabs. This aims to cement their HBM duopoly and close the gap with TSMC in advanced foundry, reshaping global AI infrastructure supply chain costs.
OpenAI and Broadcom Tape Out First Inference ASIC Jalapeño in 9 Months, Targeting NVIDIA Dominance
OpenAI and Broadcom unveil Jalapeño, their first custom inference ASIC, fabricated on TSMC 3nm and optimized for Transformer models. Targeting a 50% inference cost reduction, it taped out in 9 months and is slated for deployment in gigawatt-scale data centers by late 2026, marking OpenAI's strategic pivot to full-stack AI infrastructure and a direct challenge to NVIDIA's inference hegemony.
Google TPU v9 Switches to MediaTek, Breaking Broadcom's AI ASIC Monopoly
Google moves its TPU v9 Humufish design and integration contract from Broadcom to MediaTek, which handles I/O chip design and packaging. Combined with a split-foundry strategy (TSMC N2 compute, Samsung 2nm I/O), this marks a systematic effort to build a multi-vendor, multi-node supply chain, directly dismantling Broadcom's dominance in custom AI ASICs.