Reports
AI-generated structured vendor updates
台积电四季度3纳米月产能预计达18万片
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英伟达AMD博通追单：台积电3nm月产18万片目标有望提前至Q4初达成，2nm年底冲刺10万片
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MediaTek targets Google TPU v10 and Meta AI ASIC orders with 400G SerDes
MediaTek announces 400G/448Gbps SerDes ready by 2027, targeting Google TPU v10 and Meta AI ASIC orders. It has secured major TPU v9 orders and aims for 15-20% ASIC market share, leveraging 2nm process for data center AI chips.
MediaTek Adopts Dual Packaging: CoWoS and Intel EMIB-T for ASIC
MediaTek CEO confirms ASIC projects adopt Intel EMIB-T packaging alongside TSMC CoWoS. EMIB-T uses micro bridges for high-density interconnects, supporting HBM, achieving 8-10x reticle area at lower cost. Dual-track strategy highlights packaging as a key competitive dimension in AI chips.
TSMC Develops quasi-EMIB Packaging to Break CoWoS Capacity Bottleneck
TSMC is collaborating with Kinsus to develop quasi-EMIB advanced packaging to address severe CoWoS capacity constraints. The new approach aims to simplify manufacturing, reduce cycle time, and lower costs, bolstering TSMC's competitive position against Intel and Samsung.
Intel Accelerates Ohio Fab, Plans 14A by 2031, EMIB-T Packaging 50% Cheaper than CoWoS but Yield at 50%
Intel is accelerating its Ohio fab construction, targeting 14A process mass production by 2031. Its EMIB-T advanced packaging offers 50% cost reduction over TSMC CoWoS, but substrate yield remains at 50%, limiting scale-up. EMIB-T packaging service expected by 2027.
TSMC Develops EMIB-Like Packaging with Kinsus to Counter Intel's CoWoS Threat
TSMC, in response to CoWoS capacity constraints and potential customer loss, is developing an EMIB-like advanced packaging technology with Kinsus, aiming to simplify manufacturing steps and reduce costs, preventing clients from shifting to Intel's packaging platform, highlighting the strategic importance of advanced packaging in AI chip competition.
TSMC Accelerates 1.4nm Process, Partners with Unimicron on EMIB-Like Packaging to Counter Intel
TSMC accelerates its 1.4nm (A14) process to mid-2028 mass production, using second-gen GAA NanoFlex Pro transistors and existing EUV lithography. It also partners with Unimicron on EMIB-like packaging to alleviate CoWoS capacity constraints and prevent AI chip customer loss to Intel's packaging platform.
TSMC Develops EMIB-like Packaging to Challenge Intel and Ease CoWoS Bottleneck
TSMC is developing an EMIB-like advanced packaging technology that uses small silicon bridges instead of large silicon interposers, reducing cost and complexity while easing CoWoS capacity constraints. This move counters Intel's EMIB technology and addresses the growing packaging demands of AI accelerators, securing TSMC's dominance in advanced packaging.
台积电亚利桑那二厂主体建筑完成Q4进入设备装机阶段
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苹果M7芯片跳过M6代际直指端侧AI推理加速
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ASML Q2营收93亿欧元 High-NA EUV在Intel 18A达到生产级良率
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NVIDIA Prepay $1.5B to Amkor for US 2nm/3nm/HBM4 Advanced Packaging
NVIDIA prepays $1.5B to Amkor to expand advanced packaging capacity in Arizona, covering 2nm/3nm/HBM4. This onshores AI chip packaging, complementing Wistron's system integration, to reduce reliance on Taiwan and secure supply for Vera Rubin and Blackwell Ultra.
Intel Accelerates 14A to 2027H2 Risk Production, 18A Yield Exceeds Target by 25%, Capex Raised to $20B
Intel announced 14A process acceleration to risk production in 2027H2 with HVM in 2028, 18A yield exceeding target by 25% supporting Panther Lake volume, and raising 2026 capex to $20B, signaling an aggressive foundry push. Advanced packaging EMIB-T becomes a profit pillar.
Microsoft Azure Deploys AMD Helios Rack with MI455X GPUs, Launches Three New VM Families
Microsoft Azure announces the deployment of AMD Helios rack-scale AI platform, featuring 72 Instinct MI455X GPUs, 31TB HBM4 memory, and 1.4PB/s bandwidth per rack. Three new VM families target AI inference, data engineering, and HPC, powered by 6th-gen EPYC Venice CPUs and Pensando DPUs.
ASML Q2营收93.3亿欧元超预期，上调全年指引
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Intel与Fortinet战略合作开发SP6安全处理器，18A工艺良率提升至85%
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NVIDIA公开Rubin GPU架构细节：3360亿晶体管，智能体AI性能较Blackwell提升10倍
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TSMC Pledges $100B More for 6 US Fabs, Localizing 3nm for AI Chip Supply Chain
TSMC announces an additional $100B investment in Arizona, bringing total US commitment to $265B, with plans for 6 fabs focused on 3nm and beyond. This move localizes advanced process for AI chip demand from NVIDIA, Apple, AMD, reshaping global semiconductor supply chain. Q2 net profit surged 77% YoY, FY capex raised to $60-64B.
IBM Unveils 0.7nm Nanostack 3D Transistor, Doubling Density and Extending Moore’s Law
IBM debuts the world’s first sub-1nm chip technology at 0.7nm node using a nanostack 3D transistor architecture, packing nearly 100 billion transistors with double the density of its 2nm node. It delivers 50% performance gain or 70% energy efficiency improvement, and 40% SRAM scaling for AI workloads.