Reports
AI-generated structured vendor updates
NVIDIA and SK Hynix Lock Down HBM4/5 Roadmap, Cementing Vera Rubin Supply Chain
NVIDIA and SK Hynix sign a multi-year agreement to co-define HBM4 production and HBM5 pre-research for Vera Rubin GPUs. Samsung also enters HBM4 supply as a second source. The deal elevates SK Hynix from vendor to co-developer, potentially creating a de facto memory standard barrier that marginalizes Micron and others.
Huawei's Tao Law: LogicFolding Bypasses Lithography, 55% Density Gain on Fixed Node
At ISCAS 2026, Huawei's He Tingbo unveiled the Tao Law, replacing geometric scaling with temporal optimization targeting tau (characteristic time). LogicFolding vertically stacks active layers to shorten critical paths, achieving 55% transistor density increase and 41% energy efficiency gain on a fixed node. Kirin 2026 reaches 3.1GHz; Ascend series will adopt LogicFolding. The roadmap projects equivalent 1.4nm density by 2031, fundamentally challenging Moore's Law's lithography dependency.
Arm Partners with Malaysian University to Cultivate Semiconductor Talent for AI Era
Arm announced a collaboration with Monash University Malaysia's School of Engineering, donating IC design development boards and establishing a guest lecturer program. The initiative aims to provide students with hands-on experience in AI chip design based on Arm architecture, addressing the growing demand for advanced computing talent in the APAC region.
Apple Expands American Manufacturing Program, Bolstering Domestic AI and Sensor Supply Chains
Apple announced new partners for its American Manufacturing Program, including Bosch, Cirrus Logic, TDK, and Qnity Electronics, to shift production of critical sensors, semiconductor materials, and AI-related components to the U.S. The move involves a $400 million investment and collaborations with TSMC and GlobalFoundries to establish advanced domestic process capabilities.
TSMC Launches eFoundry Platform to Enhance Semiconductor Design Collaboration
TSMC introduces eFoundry online portal integrating design tools, IP resources, and process technology files to enhance collaboration efficiency with design customers. The platform supports advanced process design challenges through digital tools, accelerating product development from design to mass production.
TSMC Discloses 2nm and Beyond Technology Roadmap
TSMC announces its 2nm (N2) process will adopt GAAFET architecture replacing FinFET, with plans for subsequent A-series nodes. The technology targets performance and efficiency gains for HPC and mobile applications, leveraging new materials and 3D packaging for AI and 5G/6G demands.
TSMC Shifts to System-Level Foundry Services via Technology Platform Strategy
TSMC introduces a technology platform strategy combining advanced processes and 3D packaging to deliver customized semiconductor solutions for mobile, HPC, automotive, and IoT. This marks a shift from pure-play foundry to system-level solutions, enhancing customer lock-in and service barriers through vertical integration.
TSMC Launches Specialty Technology Platform for Diverse Applications
TSMC introduces a specialty technology platform integrating mature and specialty processes like BCD, HV, and CIS to provide customized semiconductor solutions for automotive, IoT, RF, and analog/power management applications. The platform addresses specific requirements for performance, reliability, and power efficiency across diverse use cases.
TSMC Launches Supplier Portal for Enhanced Supply Chain Digitalization
TSMC introduces TSMC-SUPPLY ONLINE 360, a unified online collaboration portal for its global supplier ecosystem. The platform centralizes data exchange and process integration to enhance supply chain transparency and responsiveness.
TSMC Launches TSMC-Online™ Platform to Enhance Customer Service and Transactions
TSMC has launched its TSMC-Online™ customer service platform, integrating order management, production tracking, and online transactions. It serves as the primary online portal, marking a step in digitizing customer service and optimizing supply chain processes.
TSMC Advances AI Hardware Innovation with Advanced Process and 3D Packaging
TSMC reveals AI technology research progress, focusing on N3/N2 advanced nodes and 3D Fabric heterogeneous integration. It enhances AI chip performance and efficiency through optimized transistor architecture and packaging, targeting memory bandwidth bottlenecks for cloud-to-edge AI applications.
TSMC Launches Innovation Zone to Strengthen Semiconductor Design Ecosystem
TSMC launches Innovation Zone, an online platform integrating EDA tools, IP, design services, and cloud partners to provide centralized access to design solutions. It aims to streamline design processes using TSMC's advanced nodes, reducing time-to-market and fostering innovation.
TSMC Forms Cloud Alliance to Drive Semiconductor Design to Cloud
TSMC partners with cloud providers, EDA vendors and design services to form Open Innovation Platform Cloud Alliance, building a verified cloud design solution framework. The alliance will optimize EDA tool efficiency in cloud environments and provide TSMC process-certified reference flows.
ASML Integrates Lithography and Metrology Systems in Semiconductor Manufacturing Ecosystem
ASML has built an integrated product matrix centered on lithography systems, combined with metrology and computational lithography. Its EUV and DUV scanners support advanced chip manufacturing, while YieldStar metrology and Tachyon software enable process optimization and yield control. This forms a complete semiconductor manufacturing toolchain from patterning to process control.
ASML Technology Overview: The Core of Semiconductor Manufacturing from Lithography to Metrology
ASML, a global leader in semiconductor equipment, centers its technology portfolio around the core process of lithography. This brief highlights its three key technological pillars: Lithography, Metrology & Inspection, and Computational Lithography. In lithography, ASML offers a full range from Deep Ultraviolet (DUV) to Extreme Ultraviolet (EUV) solutions. Its EUV lithography machines, utilizing 13.5-nanometer wavelength light, are critical for manufacturing advanced logic and memory chips. The technology generates plasma light by firing a high-power laser at tin droplets, coupled with precision optics and vacuum systems for nanoscale patterning. For metrology and inspection, ASML employs tools like HMI e-beam metrology to perform nanoscale inspection of post-lithography wafers for pattern fidelity, overlay accuracy, and defects, providing essential data for process control. Computational lithography, via the Tachyon software platform, uses complex algorithms and massive computing power to model and optimize between chip design (mask) and physical manufacturing. This compensates for physical effects during lithography to ensure final wafer pattern accuracy. These three technologies work in close synergy, forming a complete technological loop from design to manufacturing.
TSMC Announces Agile Intelligent Operations Strategy for Smart Manufacturing
TSMC launches an Agile Intelligent Operations strategy integrating AI analytics and automation for predictive maintenance and real-time production optimization. The strategy builds a smart manufacturing ecosystem to enhance supply chain collaboration and operational flexibility.
TSMC Launches Manufacturing Optimization with Data Analytics and Machine Learning
TSMC introduces an engineering optimization solution integrating data analytics and ML for real-time monitoring and intelligent analysis of manufacturing processes, proactively identifying anomalies to improve wafer yield. The solution focuses on systematic optimization of process parameters and equipment efficiency.
ASML System Integration Innovation Strengthens Semiconductor Manufacturing Tech Barrier
ASML drives EUV and High-NA technology through deep integration of lithography hardware, metrology systems, and computational lithography software. This systemic innovation enhances chip manufacturing precision and yield, strengthening its leadership in advanced processes.
ASML Unveils Lithography Accuracy Measurement Technology: The Key to Nanometer Control
ASML has published a technical article detailing the critical principles of "measuring accuracy" in its lithography technology. The article states that in chip manufacturing, lithography machines must transfer circuit patterns onto silicon wafers with extreme precision, and measurement is the foundation for achieving this accuracy. ASML ensures precision through its unique "alignment" and "overlay" measurement systems. The alignment system ensures precise alignment between the silicon wafer and the mask, while overlay measurement is used to assess the pattern registration accuracy between consecutive lithography layers, which is crucial for manufacturing complex 3D structures. ASML's technology can achieve sub-nanometer measurement accuracy, a core capability that continuously drives the miniaturization of chip processes (such as the evolution towards 3nm nodes and beyond). This technology is an indispensable part of ASML's advanced equipment like Extreme Ultraviolet (EUV) lithography machines, ensuring consistency and yield in mass production. **Comment**: By delving into its fundamental measurement technology, ASML once again highlights its technical moat in the semiconductor equipment field. Sub-nanometer measurement and control capabilities are the invisible cornerstone enabling the continuation of Moore's Law. For chip manufacturers and material/metrology equipment suppliers, paying attention to the evolution of such underlying precision technologies is key to anticipating the feasibility and challenges of advanced process node implementation.
ASML Discloses Core Precision Mechatronics Technology in Lithography Systems
ASML detailed the precision mechatronics foundation of its lithography systems, including ultra-precision motion control platforms, active vibration isolation, and advanced sensor feedback loops. These technologies enable nanometer-scale chip manufacturing accuracy and highlight critical system-level engineering capabilities.