Reports
AI-generated structured vendor updates
Samsung GAIA AI PC Chip Samples with Memory-Centric NPU, Targeting 50 TOPS
Samsung launches GAIA AI PC processor with 4nm process and memory-centric NPU, integrating LPDDR5X controller with NPU for near-memory computing, achieving 40% energy efficiency improvement and 50 TOPS. Certified for Microsoft Copilot+ PC, Lenovo to adopt in Q4 2026.
AWS Sells Trainium 3 Externally, Challenging NVIDIA's AI Training Chip Dominance
AWS begins external sales of its Trainium 3 AI training chip, fabricated on TSMC 3nm process, delivering 2.52 PFLOPS per chip. Early customers include Anthropic and Uber. This move directly challenges NVIDIA's dominance and marks AWS's strategic shift from cloud provider to chip vendor.
AWS boosts Trainium 3 shipments, accelerating ASIC substitution for NVIDIA GPUs
Supply chain sources indicate Amazon AWS has instructed vendors to increase Trainium 3 shipments for Q3 2026 by 20-30%. This signals strong confidence in its custom ASIC strategy to reduce dependence on NVIDIA GPUs, leveraging superior cost and power efficiency for cloud AI training.
Anthropic Starts Custom AI Chip Development, Talks Samsung 2nm, Aims for Compute Independence
Anthropic has initiated its own AI chip development and is in talks with Samsung for 2nm foundry services. The move aims to reduce reliance on NVIDIA GPUs, optimize inference costs, and strengthen its technology moat ahead of a potential IPO. It joins OpenAI, Google, and others in the custom ASIC race, signaling a shift from software to hardware competition.
NVIDIA Vera Rubin AI Platform Slated for July 2026 Shipments, Iterative Compute Upgrade
NVIDIA confirms its next-gen AI compute platform, Vera Rubin, will start shipping in July 2026 to major cloud providers like Microsoft and Google. The platform uses an advanced process node to boost AI training and inference performance, representing an iterative upgrade over Hopper and Blackwell without a fundamental architectural shift.
英伟达RTX 5080公版显卡将在BW2026限量发售，售价8299元
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Samsung Restarts 1.4nm Foundry Node, Pre-emptively Locks Equipment Supply Chain
Samsung Electronics restarts 1.4nm (SF1.4) process commercialization, ordering equipment vendors to develop tools early. The node will use High-NA EUV lithography and GAA transistors, fabbed at NRD-K campus. This move aims to catch up with TSMC and Intel, but mass production timeline remains undisclosed.
Samsung Re-accelerates 1.4nm Node R&D, Adopts High-NA EUV Lithography
Samsung Electronics is re-accelerating its 1.4nm (SF1.4) process node R&D, targeting mass production by 2028-2029. It has procured High-NA EUV lithography equipment from ASML for its NRD-K R&D complex and ordered tools for 12th-gen V-NAND with wafer stacking. The move aims to catch up with TSMC and Intel in the AI chip foundry race.
Samsung and SK Hynix Announce $300B Investment to Dominate AI Memory and Foundry
Samsung and SK Hynix announce a 10-year, 1,000 trillion won investment plan to expand HBM4 production, improve 3nm GAA yield, and build new AI chip fabs. This aims to cement their HBM duopoly and close the gap with TSMC in advanced foundry, reshaping global AI infrastructure supply chain costs.
ASML EXE:5200 High-NA EUV: 8nm Resolution Locks 2nm Node, Cost Trap Looms
ASML launches the EXE:5200 High-NA EUV lithography system, boosting resolution from 13nm to 8nm and wafer throughput to 220 WPH, enabling 2nm and beyond. Intel is the first customer for its 18A process. ASML also reveals Hyper-NA (NA 0.85) development for sub-1nm nodes.
Samsung 3nm GAA Yield Hits 80%, Lands Nvidia Order: TSMC Monopoly Challenged
Samsung Electronics announced its 3nm GAA process yield has exceeded 80%, securing orders from Nvidia for mid-range GPUs. This milestone marks the commercialization of Samsung's SF3 technology, aiming to reduce Nvidia's reliance on TSMC.
TSMC Capacity Crunch Reshapes Foundry Landscape: Google, AMD, Tesla Move to Samsung for Advanced Nodes
TSMC's advanced capacity shortage through 2027 pushes Google, AMD, and Tesla to Samsung for 3nm/2nm foundry services. Samsung's 6.5% market share may see structural growth, shifting global chip supply from single-source to multi-source, though yield and trust issues persist.
Huawei's Tao Law: LogicFolding Bypasses Lithography, 55% Density Gain on Fixed Node
At ISCAS 2026, Huawei's He Tingbo unveiled the Tao Law, replacing geometric scaling with temporal optimization targeting tau (characteristic time). LogicFolding vertically stacks active layers to shorten critical paths, achieving 55% transistor density increase and 41% energy efficiency gain on a fixed node. Kirin 2026 reaches 3.1GHz; Ascend series will adopt LogicFolding. The roadmap projects equivalent 1.4nm density by 2031, fundamentally challenging Moore's Law's lithography dependency.
TSMC Q1 Earnings: Advanced Packaging Capacity Bottleneck to Persist, Constraining AI Chip Supply Through 2025
TSMC Q1 earnings show HPC crossing 60% revenue share for the first time; CoWoS advanced packaging capacity will remain tight through 2027—the real AI chip supply bottleneck is packaging, not processes.
Apple Expands American Manufacturing Program, Bolstering Domestic AI and Sensor Supply Chains
Apple announced new partners for its American Manufacturing Program, including Bosch, Cirrus Logic, TDK, and Qnity Electronics, to shift production of critical sensors, semiconductor materials, and AI-related components to the U.S. The move involves a $400 million investment and collaborations with TSMC and GlobalFoundries to establish advanced domestic process capabilities.
TSMC Launches eFoundry Platform to Enhance Semiconductor Design Collaboration
TSMC introduces eFoundry online portal integrating design tools, IP resources, and process technology files to enhance collaboration efficiency with design customers. The platform supports advanced process design challenges through digital tools, accelerating product development from design to mass production.
TSMC Launches Mask Service to Strengthen One-Stop Chip Manufacturing
TSMC officially launches mask manufacturing service covering full process from data preparation to inspection and repair. The service integrates mask fabrication capabilities for process co-optimization and faster time-to-market. This strengthens TSMC's one-stop manufacturing solution and deepens customer collaboration.
TSMC Discloses 2nm and Beyond Technology Roadmap
TSMC announces its 2nm (N2) process will adopt GAAFET architecture replacing FinFET, with plans for subsequent A-series nodes. The technology targets performance and efficiency gains for HPC and mobile applications, leveraging new materials and 3D packaging for AI and 5G/6G demands.
TSMC Releases Advanced Process Roadmap, N2 and A16 Technologies Lead Chip Innovation
TSMC unveiled its logic process technology roadmap, highlighting advanced nodes like N2 and A16. N2 adopts GAAFET architecture for performance and power efficiency gains, while A16 integrates backside power delivery for HPC optimization, reinforcing TSMC's leadership in semiconductor manufacturing.
TSMC Launches Advanced Packaging Platform for Heterogeneous Integration
TSMC launches an advanced packaging platform integrating CoWoS, InFO, and SoIC 3D stacking technologies for micron-level vertical integration of chips across process nodes. It delivers higher interconnect density, bandwidth, and lower power consumption, supporting complex SoC designs as part of its Open Innovation Platform to accelerate time-to-market.